EDA考试用纸.docx
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EDA考试用纸
目录
-5种格式加法器1
--布尔代数法1
--usewhen_elsesentences1
--usewith_select_whensentences3
--useif_elsif_elsesentence3
--usecase_whensentence4
38译码器5
JK触发器5
D触发器6
--D所存6
--div6
-交通灯7
--jiaotongdeng7
--div_miao9
--mux29
--state_ctrl10
--scan_cnt13
--scan_div14
数码管14
--shumaguan_4714
--div15
--cnt816
--shumaguantop16
数字钟17
--count817
--fenpin19
--boma19
--shuzizhong20
点阵显示24
--点阵24
--cnt1625
--div26
-5种格式加法器
--布尔代数法
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityadder_01is
port（ai,bi,ci_1:
inbit;
si,ci:
outbit）;
endentityadder_01;
architecturebeheaveofadder_01is
begin
si<=ci_1xor（aixorbi）;
ci<=（aiandbi）or（ci_1and（aixorbi））;
endarchitecturebeheave;
--usewhen_elsesentences
libraryieee;
useieee.std_logic_1164.all;
entityadder_02is
port（ai,bi,ci_1:
instd_logic;
si,ci:
outstd_logic）;
endentityadder_02;
architecturebeheaveofadder_02is
signaln2:
std_logic_vector（1downto0）;
signaln3:
std_logic_vector（2downto0）;
begin
n3<=ci_1&ai&bi;
n2<="00"whenn3="000"else
"10"whenn3="001"else
"10"whenn3="010"else
"01"whenn3="011"else
"10"whenn3="100"else
"01"whenn3="101"else
"01"whenn3="110"else
"11";
si<=n2
（1）;
ci<=n2（0）;
endbeheave;
--usewith_select_whensentences
libraryieee;
useieee.std_logic_1164.all;
entityadder_03is
port（ai,bi,ci_1:
instd_logic;
si,ci:
outstd_logic）;
endentityadder_03;
architecturedataflowofadder_03is
signaln2:
std_logic_vector（1downto0）;
signaln3:
std_logic_vector（2downto0）;
begin
n3<=ci_1&ai&bi;
withn3select
n2<="00"when"000",
"10"when"001",
"10"when"010",
"01"when"011",
"10"when"100",
"01"when"101",
"01"when"110",
"11"whenothers;
si<=n2
（1）;
ci<=n2（0）;
enddataflow;
--useif_elsif_elsesentence
libraryieee;
useieee.std_logic_1164.all;
entityadder_04is
port（ai,bi,ci_1:
instd_logic;
si,ci:
outstd_logic）;
endentityadder_04;
architecturebeheaveofadder_04is
signaln3:
std_logic_vector（2downto0）;
signaln2:
std_logic_vector（1downto0）;
begin
n3<=ci_1&ai&bi;
process（n3）
begin
ifn3="000"thenn2<="00";
elsifn3="001"thenn2<="10";
elsifn3="010"thenn2<="10";
elsifn3="011"thenn2<="01";
elsifn3="100"thenn2<="10";
elsifn3="101"thenn2<="01";
elsifn3="110"thenn2<="01";
elsen2<="11";
endif;
si<=n2
（1）;
ci<=n2（0）;
endprocess;
endbeheave;
--usecase_whensentence
libraryieee;
useieee.std_logic_1164.all;
entityadder_05is
port（ai,bi,ci_1:
instd_logic;
si,ci:
outstd_logic）;
endentityadder_05;
architecturebeheaveofadder_05is
signaln3:
std_logic_vector（2downto0）;
signaln2:
std_logic_vector（1downto0）;
begin
n3<=ci_1&ai&bi;
process（n3）
begin
casen3is
when"000"=>n2<="00";
when"001"=>n2<="10";
when"010"=>n2<="10";
when"011"=>n2<="01";
when"100"=>n2<="10";
when"101"=>n2<="01";
when"110"=>n2<="01";
whenothers=>n2<="11";
endcase;
si<=n2
（1）;
ci<=n2（0）;
endprocess;
endbeheave;
38译码器
libraryieee;
useieee.std_logic_1164.all;
entitydecoderis
port（inp:
instd_logic_vector（2downto0）;
outp:
outstd_logic_vector（7downto0））;
enddecoder;
architecturebehaveofdecoderis
begin
outp（0）<='1'wheninp="000"else'0';
outp
（1）<='1'wheninp="001"else'0';
outp
（2）<='1'wheninp="010"else'0';
outp（3）<='1'wheninp="011"else'0';
outp（4）<='1'wheninp="100"else'0';
outp（5）<='1'wheninp="101"else'0';
outp（6）<='1'wheninp="110"else'0';
outp（7）<='1'wheninp="111"else'0';
endbehave;
JK触发器
libraryieee;
useieee.std_logic_1164.all;
entityJKis
port（j,k,sd,rd,clk:
instd_logic;
qo,qbo:
outstd_logic）;
endJK;
architecturebehaveofJKis
signalq,qb:
std_logic;
begin
process（sd,rd,clk,q,qb）
begin
if（sd='0'andrd='1'）then
q<='1';qb<='0';
elsif（sd='1'andrd='0'）then
q<='0';qb<='1';
--elsif（sd='1'andrd='1'andclk='1'）then
--q<=q;qb<=notq;
--elsif（sd='1'andrd='1'andclk='0'）then
--q<=q;qb<=notq;
elsif（sd='1'andrd='1'andrising_edge（clk））then
q<=（jand（notq））or（（notk）andq）;
qb<=notq;
endif;
qo<=q;qbo<=qb;
endprocess;
endbehave;
D触发器
--D所存
libraryieee;
useieee.std_logic_1164.all;
entityD_suochunis
port（d,clk:
instd_logic;
q:
outstd_logic）;
endD_suochun;
architecturebehaveofD_suochunis
begin
process（clk）
begin
if（rising_edge（clk））
thenq<=d;
endif;
endprocess;
endbehave;
--div
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitydiv_1is
port（
clk20m:
instd_logic;
clkout:
outstd_logic
）;
enddiv_1;
architecturebhvofdiv_1is
signaln:
std_logic_vector（24downto0）;
begin
process（clk20m）
begin
ifrising_edge（clk20m）then
ifn=20000000then
n<=（others=>'0'）;
elsen<=n+1;
endif;
ifn<10000000then
clkout<='0';
elseclkout<='1';
endif;
endif;
endprocess;
endbhv;
-交通灯
--jiaotongdeng
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityjiaotongdengis
port（
clk:
instd_logic;
rst_n:
instd_logic;
seg_out:
outstd_logic_vector（7downto0）;
dig_out:
bufferstd_logic_vector（2downto0）;
led_out:
bufferstd_logic_vector（11downto0））;
endjiaotongdeng;
architecturebehaveofjiaotongdengis
componentscan_divis
port（
clk:
instd_logic;
scan_clk:
outstd_logic）;
endcomponent;
componentdiv_miaois
port（
clk:
instd_logic;
miao_clk:
outstd_logic）;
endcomponent;
componentscan_cntis
port（
scan_clk:
instd_logic;
dig_out:
bufferstd_logic_vector（2downto0））;
endcomponent;
componentstate_ctrlis
port（
miao_clk:
instd_logic;
rst_n:
instd_logic;
seg_out1:
outstd_logic_vector（7downto0）;
seg_out2:
outstd_logic_vector（7downto0）;
led_out:
outstd_logic_vector（11downto0））;
endcomponent;
componentmux_2is
port（
seg_out1:
instd_logic_vector（7downto0）;
seg_out2:
instd_logic_vector（7downto0）;
sel:
instd_logic_vector（2downto0）;
seg_out:
outstd_logic_vector（7downto0）
）;
endcomponent;
signalscan_clk:
std_logic;
signalmiao_clk:
std_logic;
signalseg_out1:
std_logic_vector（7downto0）;
signalseg_out2:
std_logic_vector（7downto0）;
begin
U1:
scan_divportmap（clk=>clk,scan_clk=>scan_clk）;
U2:
div_miaoportmap（clk=>clk,miao_clk=>miao_clk）;
U3:
scan_cntportmap（scan_clk=>scan_clk,dig_out=>dig_out）;
U4:
state_ctrlportmap（miao_clk=>miao_clk,rst_n=>rst_n,seg_out1=>seg_out1,
seg_out2=>seg_out2,led_out=>led_out）;
U5:
mux_2portmap（seg_out1=>seg_out1,seg_out2=>seg_out2,sel=>dig_out,seg_out=>seg_out）;
endbehave;
--div_miao
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitydiv_miaois
port（
clk:
instd_logic;
miao_clk:
outstd_logic）;
enddiv_miao;
architecturebehaveofdiv_miaois
signalcnt:
std_logic_vector（27downto0）;
begin
process（clk）
begin
ifclk'eventandclk='1'then
if（cnt=10000000-1）then
cnt<=（others=>'0'）;
else
cnt<=cnt+1;
endif;
ifcnt<5000000then
miao_clk<='1';
else
miao_clk<='0';
endif;
endif;
endprocess;
endbehave;
--mux2
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitymux_2is
port（
seg_out1:
instd_logic_vector（7downto0）;
seg_out2:
instd_logic_vector（7downto0）;
sel:
instd_logic_vector（2downto0）;
seg_out:
outstd_logic_vector（7downto0）
）;
endmux_2;
architecturebehaveofmux_2is
begin
process（sel）
begin
caseselis
when"000"=>seg_out<=seg_out1;
when"001"=>seg_out<=seg_out2;
whenothers=>seg_out<="10111111";
endcase;
endprocess;
endbehave;
--state_ctrl
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entitystate_ctrlis
port（
miao_clk:
instd_logic;
rst_n:
instd_logic;
seg_out1:
outstd_logic_vector（7downto0）;
seg_out2:
outstd_logic_vector（7downto0）;
led_out:
outstd_logic_vector（11downto0））;
endstate_ctrl;
architecturebehaveofstate_ctrlis
signalqh:
std_logic_vector（3downto0）;
signalql:
std_logic_vector（3downto0）;
typestate_typeis（s0,s1,s2,s3）;
signalstate:
state_type;
begin
process（miao_clk）
begin
if（rst_n='0'）then
state<=s0;
qh<="0011";
ql<="0100";
led_out<="100001100001";
elsifmiao_clk'eventandmiao_clk='1'then
casestateis
whens0=>if（ql=0）then
ql<="1001";
if（qh=0）then
state<=s1;
led_out<="010001010001";
qh<="0000";
ql<="0010";
else
qh<=qh-1;
endif;
else
ql<=ql-1;
state<=s0;
endif;
whens1=>if（ql=0）then
ql<="1001";
if（qh=0）then
state<=s2;
led_out<="001100001100";
qh<="0101";
ql<="1001";
else
qh<=qh-1;
endif;
else
ql<=ql-1;
state<=s1;
endif;
whens2=>if（ql=0）then
ql<="1001";
if（qh=0）then
state<=s3;
led_out<="001010001010";
qh<="0000";
ql<="0010";
else
qh<=qh-1;
endif;
else
ql<=ql-1;
state<=s2;
endif;
whens3=>if（ql=0）then
ql<="1001";
if（qh=0）then
state<=s0;
led_out<="100001100001";
qh<="0011";
ql<="0100";
else
qh<=qh-1;
endif;
else
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