EDA考试用纸.docx

1、EDA考试用纸目录-5种格式加法器 1-布尔代数法 1-use when_else sentences 1-use with_select_when sentences 3-use if_elsif_else sentence 3-use case_when sentence 438译码器 5JK触发器 5D触发器 6-D所存 6-div 6-交通灯 7-jiaotongdeng 7-div_miao 9-mux2 9-state_ctrl 10- scan_cnt 13-scan_div 14数码管 14-shumaguan_47 14-div 15-cnt8 16-shumaguan to

2、p 16数字钟 17-count8 17-fenpin 19-boma 19-shuzizhong 20点阵显示 24-点阵 24-cnt16 25-div 26 -5种格式加法器-布尔代数法library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity adder_01 is port( ai,bi,ci_1:in bit; si,ci:out bit); end entity adder_01;architecture beheave of adder_01 is begin si=ci_1 x

3、or ( ai xor bi ); ci=(ai and bi) or (ci_1 and ( ai xor bi ) ; end architecture beheave ;-use when_else sentenceslibrary ieee;use ieee.std_logic_1164.all;entity adder_02 isport( ai,bi,ci_1:in std_logic; si,ci:out std_logic ); end entity adder_02;architecture beheave of adder_02 issignal n2:std_logic_

4、vector(1 downto 0);signal n3:std_logic_vector(2 downto 0); begin n3 = ci_1 & ai & bi; n2=00 when n3=000 else 10 when n3=001 else 10 when n3=010 else 01 when n3=011 else 10 when n3=100 else 01 when n3=101 else 01 when n3=110 else 11 ; si=n2(1); ci=n2(0); end beheave;-use with_select_when sentenceslib

5、rary ieee;use ieee.std_logic_1164.all;entity adder_03 is port( ai,bi,ci_1:in std_logic; si,ci:out std_logic); end entity adder_03 ;architecture dataflow of adder_03 is signal n2:std_logic_vector(1 downto 0);signal n3:std_logic_vector(2 downto 0); begin n3=ci_1 & ai & bi ; with n3 select n2=00 when 0

6、00, 10 when 001, 10 when 010, 01 when 011, 10 when 100, 01 when 101, 01 when 110, 11 when others; si=n2(1); ci=n2(0); end dataflow;-use if_elsif_else sentencelibrary ieee;use ieee.std_logic_1164.all;entity adder_04 isport ( ai,bi,ci_1:in std_logic ; si,ci:out std_logic ) ; end entity adder_04 ; arch

7、itecture beheave of adder_04 is signal n3:std_logic_vector(2 downto 0); signal n2:std_logic_vector(1 downto 0);begin n3= ci_1 & ai & bi ; process ( n3 ) begin if n3=000 then n2=00; elsif n3=001 then n2=10; elsif n3=010 then n2=10; elsif n3=011 then n2=01; elsif n3=100 then n2=10; elsif n3=101 then n

8、2=01; elsif n3=110 then n2=01; else n2=11; end if; si=n2(1); ci=n2(0); end process; end beheave;-use case_when sentencelibrary ieee;use ieee.std_logic_1164.all;entity adder_05 is port ( ai,bi,ci_1:in std_logic ; si,ci:out std_logic); end entity adder_05; architecture beheave of adder_05 is signal n3

9、:std_logic_vector(2 downto 0);signal n2:std_logic_vector(1 downto 0);begin n3 n2 n2 n2 n2 n2 n2 n2 n2=11; end case ; si=n2(1); ci=n2(0); end process; end beheave;38译码器library ieee;use ieee.std_logic_1164.all;entity decoder is port ( inp: in std_logic_vector(2 downto 0); outp: out std_logic_vector(7

10、downto 0);end decoder;architecture behave of decoder is beginoutp(0) = 1 when inp = 000 else 0;outp(1) = 1 when inp = 001 else 0;outp(2) = 1 when inp = 010 else 0;outp(3) = 1 when inp = 011 else 0;outp(4) = 1 when inp = 100 else 0;outp(5) = 1 when inp = 101 else 0;outp(6) = 1 when inp = 110 else 0;o

11、utp(7) = 1 when inp = 111 else 0;end behave;JK触发器library ieee;use ieee.std_logic_1164.all;entity JK is port (j,k,sd,rd,clk: in std_logic; qo,qbo: out std_logic);end JK;architecture behave of JK issignal q,qb : std_logic;begin process(sd,rd,clk,q,qb) begin if (sd=0 and rd=1) then q=1;qb=0; elsif (sd=

12、1 and rd=0) then q=0;qb=1; - elsif (sd=1 and rd=1 and clk=1 ) then - q=q; qb=not q; -elsif (sd=1 and rd=1 and clk=0 ) then - q=q; qb=not q; elsif (sd=1 and rd=1 and rising_edge(clk) then q=(j and (not q) or (not k)and q); qb=not q; end if;qo=q; qbo=qb; end process;end behave;D触发器-D所存library ieee;use

13、 ieee.std_logic_1164.all; entity D_suochun isport( d,clk:in std_logic; q :out std_logic);end D_suochun;architecture behave of D_suochun is begin process (clk) begin if (rising_edge(clk) then q=d; end if; end process;end behave;-divlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.

14、all;entity div_1 isport ( clk20m :in std_logic; clkout :out std_logic ); end div_1;architecture bhv of div_1 is signal n :std_logic_vector(24 downto 0);begin process(clk20m) begin if rising_edge(clk20m) then if n=20000000 then n0); else n=n+1; end if; if n10000000 then clkout=0; else clkout clk,scan

15、_clk = scan_clk);U2 : div_miao port map(clk = clk,miao_clk = miao_clk);U3 : scan_cnt port map(scan_clk = scan_clk,dig_out = dig_out);U4 : state_ctrl port map(miao_clk = miao_clk,rst_n = rst_n,seg_out1 = seg_out1, seg_out2 = seg_out2,led_out = led_out);U5 : mux_2 port map(seg_out1 = seg_out1,seg_out2

16、 = seg_out2,sel = dig_out,seg_out = seg_out);end behave;-div_miao library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity div_miao isport ( clk : in std_logic; miao_clk : out std_logic);end div_miao;architecture behave of div_miao issignal cnt : s

17、td_logic_vector(27 downto 0);begin process(clk) begin if clkevent and clk = 1 then if(cnt = 10000000-1) then cnt 0); else cnt = cnt + 1; end if; if cnt 5000000 then miao_clk = 1; else miao_clk seg_out seg_out seg_out = 10111111; end case; end process; end behave;-state_ctrllibrary ieee;use ieee.std_

18、logic_1164.all;use ieee.std_logic_unsigned.all;use ieee.std_logic_arith.all;entity state_ctrl isport ( miao_clk : in std_logic; rst_n : in std_logic; seg_out1 : out std_logic_vector(7 downto 0); seg_out2 : out std_logic_vector(7 downto 0); led_out : out std_logic_vector(11 downto 0);end state_ctrl;a

19、rchitecture behave of state_ctrl issignal qh : std_logic_vector(3 downto 0);signal ql : std_logic_vector(3 downto 0);type state_type is(s0,s1,s2,s3);signal state : state_type;begin process(miao_clk) begin if(rst_n = 0) then state = s0; qh = 0011; ql = 0100; led_out if(ql = 0) then ql = 1001; if(qh =

20、 0) then state = s1; led_out = 010001010001; qh = 0000; ql = 0010; else qh = qh - 1; end if; else ql = ql - 1; state if(ql = 0) then ql = 1001; if(qh = 0) then state = s2; led_out = 001100001100; qh = 0101; ql = 1001; else qh = qh - 1; end if; else ql = ql - 1; state if(ql = 0) then ql = 1001; if(qh = 0) then state = s3; led_out = 001010001010; qh = 0000; ql = 0010; else qh = qh - 1; end if; else ql = ql - 1; state if(ql = 0) then ql = 1001; if(qh = 0) then state = s0; led_out = 100001100001; qh = 0011; ql = 0100; else qh = qh - 1; end if; else