数字钟.docx
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数字钟
用faga设计数字钟
要求：
走时，可以调整时间，整点报时（蜂鸣器响）
1.Shuzizhong.vhd
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useIEEE.STD_LOGIC_ARITH.ALL;
entityshuzizhongis
port（
clk_change:
instd_logic;
s_en,m_en,h_en:
instd_logic;
sel:
instd_logic;
secout,minout,hourout:
outstd_logic;
sl,sh,ml,mh,hl,hh:
outstd_logic_vector（3downto0）;
a:
outstd_logic_vector（15downto0）
）;
endshuzizhong;
architecturebehavofshuzizhongis
signallow_rega,high_rega,low_regb,high_regb,low_regc,high_regc:
std_logic_vector（3downto0）:
="0000";
signalsout,mout,hout:
std_logic:
='0';
begin
--秒的60进制进制
counter_sec_l:
process（clk_change,s_en）
begin
sl<=low_rega;sh<=high_rega;ml<=low_regb;mh<=high_regb;hl<=low_regc;hh<=high_regc;
ifclk_change'eventandclk_change='1'then
ifs_en='1'then
iflow_rega="1001"then
low_rega<="0000";
else
low_rega<=low_rega+'1';
endif;
endif;
endif;
endprocesscounter_sec_l;
counter_sec_h:
process（clk_change,s_en,low_rega）
begin
ifclk_change'eventandclk_change='1'then
ifs_en='1'then
iflow_rega="1001"then
ifhigh_rega="0101"then
high_rega<="0000";
else
high_rega<=high_rega+'1';
endif;
endif;
endif;
endif;
endprocesscounter_sec_h;
sout<='1'whenlow_rega="1001"andhigh_rega="0101"else'0';
----分钟的60进制设置
counter_min_l:
process（clk_change,m_en）
begin
ifclk_change'eventandclk_change='1'then
ifm_en='1'then
ifsout='1'orsel='0'then
iflow_regb="1001"then
low_regb<="0000";
else
low_regb<=low_regb+'1';
endif;
endif;
endif;
endif;
endprocesscounter_min_l;
counter_min_h:
process（clk_change,m_en,low_regb）
begin
ifclk_change'eventandclk_change='1'then
ifsout='1'orsel='0'then
ifm_en='1'then
iflow_regb="1001"then
ifhigh_regb="0101"then
high_regb<="0000";
else
high_regb<=high_regb+'1';
endif;
endif;
endif;
endif;
endif;
endprocesscounter_min_h;
mout<='1'whenlow_regb="1001"andhigh_regb="0101"andsout='1'else'0';
--小时的24进制设置
counter_hour_l:
process（clk_change,h_en）
begin
ifclk_change'eventandclk_change='1'then
ifh_en='1'then
ifmout='1'orsel='0'then
iflow_regc="1001"orhout='1'then
low_regc<="0000";
else
low_regc<=low_regc+'1';
endif;
endif;
endif;
endif;
endprocesscounter_hour_l;
counter_hour_h:
process（clk_change,h_en,hout）
begin
ifclk_change'eventandclk_change='1'then
ifmout='1'orsel='0'then
ifh_en='1'then
ifhout='1'then
high_regc<="0000";
elseiflow_regc="1001"then
high_regc<=high_regc+'1';
endif;
endif;
endif;
endif;
endif;
endprocesscounter_hour_h;
hout<='1'whenlow_regc="0011"andhigh_regc="0010"else'0';
secout<=sout;minout<=mout;hourout<=hout;
a<=high_regb&low_regb&high_rega&low_rega;
endbehav;
2.Baoshi.vhd
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useIEEE.STD_LOGIC_ARITH.ALL;
--整点报时
entitybaoshiis
port（
a:
instd_logic_vector（15downto0）;
d:
outstd_logic_vector（4downto0））;
endbaoshi;
architecturezhongofbaoshiis
signalled:
std_logic_vector（4downto0）;
begin
process（led）
begin
caseais
when"0101100101010110"=>led<="00001";
when"0101100101010111"=>led<="00011";
when"0101100101011000"=>led<="00111";
when"0101100101011001"=>led<="01111";
when"0000000000000000"=>led<="11111";
whenothers=>led<=NULL;
endcase;
endprocess;
d<=led;
endzhong;
3.Display.vhd
libraryieee;
useieee.std_logic_1164.all;
entitydisplayis
port（
datain:
instd_logic_vector（3downto0）;
dataout:
outstd_logic_vector（6downto0））;
enddisplay;
architectureduanofdisplayis
begin
process（datain）
begin
casedatainis
when"0000"=>dataout<="1000000";--dp,g,f,e,d,c,b,a
when"0001"=>dataout<="1111001";
when"0010"=>dataout<="0100100";
when"0011"=>dataout<="0110000";
when"0100"=>dataout<="0011001";
when"0101"=>dataout<="0010010";
when"0110"=>dataout<="0000010";
when"0111"=>dataout<="1111000";
when"1000"=>dataout<="0000000";
when"1001"=>dataout<="0010000";
when"1010"=>dataout<="0111111";
when"1011"=>dataout<="0000011";
when"1100"=>dataout<="0100111";
when"1101"=>dataout<="0100001";
when"1110"=>dataout<="0000110";
when"1111"=>dataout<="0001110";
whenothers=>null;
endcase;
endprocess;
end;
4.Fre.vhd
libraryieee;
useieee.std_logic_1164.all;
entityfreis
port（
clk,sel:
instd_logic;
clk1hz,clk1khz,clk2khz:
outstd_logic）;
endfre;
architecturebehoffreis
signaldata1khz,data2khz,data1hz:
std_logic:
='0';
begin
clk1hz<=data1hz;
clk1khz<=data1khz;
clk2khz<=data2khz;
clk1khz_pro:
process（clk）--产生1khz信号
variablecnt:
integerrange0to24999;
begin
ifclk'eventandclk='1'then
ifcnt=24999then
cnt:
=0;data1khz<=notdata1khz;
else
cnt:
=cnt+1;
endif;
endif;
endprocessclk1khz_pro;
clk2khz_pro:
process（clk）--产生2khz信号
variablecnt:
integerrange0to12499;
begin
ifclk'eventandclk='1'then
ifcnt=12499then
cnt:
=0;data2khz<=notdata2khz;
else
cnt:
=cnt+1;
endif;
endif;
endprocessclk2khz_pro;
clk1hz_pro:
process（data1khz）--产生1hz信号
variablecnt:
integerrange0to499;
begin
ifdata1khz'eventanddata1khz='1'then
ifsel='0'thencnt:
=0;
elseifcnt=499then
cnt:
=0;data1hz<=notdata1hz;
else
cnt:
=cnt+1;
endif;
endif;
endif;
endprocessclk1hz_pro;
endbeh;
5.key_press.vhd
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitykey_pressis
port（set,mode:
instd_logic;
clk1khz,clk1hz:
instd_logic;
secout,minout:
instd_logic;
clk_change,clk2hz_en:
outstd_logic;
sel,s_ce,m_ce,h_ce:
outstd_logic;
s_en,m_en,h_en:
outstd_logic）;
endkey_press;
architecturebehofkey_pressis
signalkey1,key2:
std_logic;
signalsce_reg,mce_reg,hce_reg:
std_logic;
signalssl,ssen,mmen,hhen:
std_logic;
signalcon:
integerrange0to4:
=0;
--按键按下（延时）
begin
key_press2:
process（set,clk1khz）
variablecnt:
integerrange0to999;
begin
ifset='0'then
ifclk1khz'eventandclk1khz='1'then
ifcnt=50andset='0'then
cnt:
=cnt+1;key2<='1';
elsecnt:
=cnt+1;key2<='0';
endif;
endif;
else
cnt:
=0;key2<='0';
endif;
endprocesskey_press2;
key_press1:
process（mode,clk1khz）
variablecnt:
integerrange0to999;
begin
ifmode='0'then
ifclk1khz'eventandclk1khz='1'then
ifcnt=50andmode='0'then
cnt:
=cnt+1;key1<='1';
elsecnt:
=cnt+1;key1<='0';
endif;
endif;
else
cnt:
=0;key1<='0';
endif;
endprocesskey_press1;
count:
process（key1,key2）
begin
ifkey1'eventandkey1='1'then
ifcon=4then
con<=0;
else
con<=con+1;
endif;
endif;
endprocesscount;
con_pro:
process（con）
begin
caseconis
when0=>ssl<='1';
sce_reg<='0';ssen<='1';
mce_reg<='0';mmen<='1';
hce_reg<='0';hhen<='1';
clk2hz_en<='0';
when1=>ssl<='0';
sce_reg<='0';ssen<='1';
mce_reg<='0';mmen<='1';
hce_reg<='0';hhen<='1';
clk2hz_en<='1';
when2=>ssl<='0';
sce_reg<='1';ssen<='1';
mce_reg<='0';mmen<='0';
hce_reg<='0';hhen<='0';
clk2hz_en<='1';
when3=>ssl<='0';
sce_reg<='0';ssen<='0';
mce_reg<='1';mmen<='1';
hce_reg<='0';hhen<='0';
clk2hz_en<='1';
when4=>ssl<='0';
sce_reg<='0';ssen<='0';
mce_reg<='0';mmen<='0';
hce_reg<='1';hhen<='1';
clk2hz_en<='1';
whenothers=>ssl<='0';
sce_reg<='0';ssen<='1';
mce_reg<='0';mmen<='1';
hce_reg<='0';hhen<='1';
clk2hz_en<='0';
endcase;
endprocesscon_pro;
sel_pro:
process（ssl）
begin
casesslis
when'0'=>s_ce<=sce_reg;
m_ce<=mce_reg;
h_ce<=hce_reg;
clk_change<=key2;
when'1'=>s_ce<=ssen;
m_ce<=mmen;
h_ce<=hhen;
clk_change<=clk1hz;
whenothers=>s_ce<=ssen;
m_ce<=secout;
h_ce<=minout;
clk_change<=clk1hz;
endcase;
endprocesssel_pro;
sel<=ssl;s_en<=ssen;m_en<=mmen;h_en<=hhen;
endbeh;
6.Scan.vhd
libraryieee;
useieee.std_logic_1164.all;
entityscanis
port（
clk1khz:
instd_logic;
sl,sh,ml,mh,hl,hh:
instd_logic_vector（3downto0）;
clk2hz_en:
instd_logic;
s_ce,m_ce,h_ce:
instd_logic;
en_out:
outstd_logic_vector（7downto0）;
dataout:
outstd_logic_vector（3downto0））;
endscan;
architecturebehofscanis
signalcnt:
integerrange0to7;
signalen:
std_logic_vector（7downto0）;
signalclk2hz:
std_logic;
signalh_ce_reg,m_ce_reg,s_ce_reg:
std_logic;
begin
h_ce_reg<=noth_ce;
m_ce_reg<=notm_ce;
s_ce_reg<=nots_ce;
cnt_pro:
process（clk1khz）
begin
ifclk1khz'eventandclk1khz='1'then
ifcnt=7then
cnt<=0;
else
cnt<=cnt+1;
endif;
endif;
endprocesscnt_pro;
clk2hz_pro:
process（clk1khz）
variablec:
integerrange0to499:
=0;
begin
ifclk1khz'eventandclk1khz='1'then
ifclk2hz_en='1'then
ifc=499then
c:
=0;clk2hz<=notclk2hz;
else
c:
=c+1;
endif;
else
clk2hz<='0';
endif;
endif;
endprocessclk2hz_pro;
scan_pro:
process（cnt,sl,sh,ml,mh,hl,hh）
begin
casecntis
when0=>dataout<=sl;en<="11111110";
when1=>dataout<=sh;en<="11111101";
when2=>dataout<=ml;en<="11110111";
when3=>dataout<=mh;en<="11101111";
when4=>dataout<=hl;en<="10111111";
when5=>dataout<=hh;en<="01111111";
when6=>dataout<="1010";en<="11111011";
when7=>dataout<="1010";en<="11011111";
whenothers=>null;
endcase;
endprocessscan_pro;
en_out<=enor（（clk2hz&clk2hz）or（h_ce_reg&h_ce_reg））&clk2hz&（（clk2hz&clk2hz）or（m_ce_reg&m_ce_reg））&clk2hz&（（clk2hz&clk2hz）or（s_ce_reg&s_ce_reg））;
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