数字钟.docx

1、数字钟 用faga设计数字钟要求：走时，可以调整时间，整点报时（蜂鸣器响）1.Shuzizhong.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;use IEEE.STD_LOGIC_ARITH.ALL;entity shuzizhong isport(clk_change : in std_logic;s_en,m_en,h_en:in std_logic;sel:in std_logic;secout,minout,hourout :out std_logic;sl,sh,ml,mh,

2、hl,hh:out std_logic_vector(3 downto 0);a:out std_logic_vector(15downto 0);end shuzizhong;architecture behav of shuzizhong issignal low_rega,high_rega,low_regb,high_regb,low_regc,high_regc :std_logic_vector(3 downto 0):=0000;signal sout,mout,hout :std_logic :=0;begin-秒的60进制进制 counter_sec_l : process(

3、clk_change,s_en) begin sl=low_rega;sh=high_rega;ml=low_regb;mh=high_regb;hl=low_regc;hh=high_regc; if clk_changeevent and clk_change=1 then if s_en=1 then if low_rega=1001 then low_rega = 0000; else low_rega = low_rega+1; end if; end if; end if; end process counter_sec_l; counter_sec_h : process(clk

4、_change,s_en,low_rega) begin if clk_changeevent and clk_change=1 then if s_en=1 then if low_rega=1001 then if high_rega =0101then high_rega = 0000; else high_rega = high_rega+1; end if; end if; end if; end if; end process counter_sec_h; sout = 1 when low_rega=1001 and high_rega=0101 else 0; -分钟的60进制

5、设置 counter_min_l : process(clk_change,m_en) begin if clk_changeevent and clk_change=1 then if m_en=1 then if sout=1or sel=0 then if low_regb=1001 then low_regb = 0000; else low_regb = low_regb+1; end if; end if; end if; end if; end process counter_min_l; counter_min_h : process(clk_change,m_en,low_r

6、egb) begin if clk_changeevent and clk_change=1 then if sout=1or sel=0 then if m_en=1 then if low_regb=1001 then if high_regb =0101then high_regb = 0000; else high_regb = high_regb+1; end if; end if; end if; end if; end if; end process counter_min_h; mout = 1 when low_regb=1001 and high_regb=0101and

7、sout=1 else 0; -小时的24进制设置counter_hour_l : process(clk_change,h_en) begin if clk_changeevent and clk_change=1 then if h_en=1 then if mout=1or sel=0 then if low_regc=1001or hout=1 then low_regc = 0000; else low_regc = low_regc+1; end if; end if; end if; end if; end process counter_hour_l; counter_hour

8、_h : process(clk_change,h_en,hout) begin if clk_changeevent and clk_change=1 then if mout=1or sel=0 then if h_en=1 then if hout=1 then high_regc=0000; else if low_regc=1001 then high_regc = high_regc+1; end if; end if; end if; end if; end if; end process counter_hour_h; hout = 1 when low_regc=0011 a

9、nd high_regc=0010 else 0; secout=sout;minout=mout;hourout=hout; a led led led led led led=NULL; end case; end process ; d dataout dataout dataout dataout dataout dataout dataout dataout dataout dataout dataout dataout dataout dataout dataout dataout null; end case; end process; end ;4.Fre.vhdlibrary

10、 ieee;use ieee.std_logic_1164.all;entity fre isport(clk ,sel: in std_logic;clk1hz,clk1khz,clk2khz:out std_logic);end fre;architecture beh of fre issignal data1khz,data2khz,data1hz : std_logic := 0;begin clk1hz = data1hz; clk1khz = data1khz; clk2khz = data2khz; clk1khz_pro : process(clk) -产生1khz信号 va

11、riable cnt : integer range 0 to 24999; begin if clkevent and clk=1 then if cnt = 24999 then cnt := 0 ; data1khz = not data1khz; else cnt := cnt + 1; end if; end if; end process clk1khz_pro; clk2khz_pro : process(clk) -产生2khz信号 variable cnt : integer range 0 to 12499; begin if clkevent and clk=1 then

12、 if cnt = 12499 then cnt := 0 ; data2khz = not data2khz; else cnt := cnt + 1; end if; end if; end process clk2khz_pro; clk1hz_pro : process(data1khz) -产生1hz 信号 variable cnt : integer range 0 to 499; begin if data1khzevent and data1khz=1 then if sel=0 then cnt:=0; else if cnt = 499 then cnt := 0 ;dat

13、a1hz = not data1hz ; else cnt := cnt + 1; end if; end if; end if; end process clk1hz_pro; end beh;5.key_press.vhdlibrary ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity key_press isport( set ,mode: in std_logic; clk1khz,clk1hz: in std_logic; secout,minout: in std_logic; clk_c

14、hange,clk2hz_en:out std_logic ; sel,s_ce,m_ce,h_ce:out std_logic; s_en,m_en,h_en:out std_logic ); end key_press; architecture beh of key_press is signal key1,key2:std_logic; signal sce_reg, mce_reg ,hce_reg:std_logic ; signal ssl,ssen,mmen,hhen:std_logic; signal con : integer range 0 to 4 :=0; -按键按下

15、（延时） begin key_press2 : process(set,clk1khz) variable cnt :integer range 0 to 999; begin if set=0 then if clk1khzevent and clk1khz=1then if cnt=50 and set=0 then cnt :=cnt+1; key2 = 1; else cnt:=cnt+1;key2 = 0; end if; end if; else cnt:=0; key2=0; end if; end process key_press2; key_press1 : process

16、(mode,clk1khz) variable cnt :integer range 0 to 999; begin if mode=0 then if clk1khzevent and clk1khz=1then if cnt=50 and mode=0 then cnt :=cnt+1; key1 = 1; else cnt:=cnt+1;key1 = 0; end if; end if; else cnt:=0; key1=0; end if; end process key_press1; count : process(key1,key2) begin if key1event an

17、d key1=1 then if con=4 then con=0; else con ssl=1; sce_reg = 0;ssen =1; mce_reg = 0;mmen =1; hce_reg = 0;hhen =1; clk2hz_en ssl=0; sce_reg = 0;ssen =1; mce_reg = 0;mmen =1; hce_reg = 0;hhen =1; clk2hz_en ssl=0; sce_reg = 1;ssen =1; mce_reg = 0;mmen =0; hce_reg = 0;hhen =0; clk2hz_en ssl=0; sce_reg =

18、 0;ssen =0; mce_reg = 1;mmen =1; hce_reg = 0;hhen =0; clk2hz_en ssl=0; sce_reg = 0;ssen =0; mce_reg = 0;mmen =0; hce_reg = 1;hhen =1; clk2hz_en ssl=0; sce_reg = 0;ssen =1; mce_reg = 0;mmen =1; hce_reg = 0;hhen =1; clk2hz_en s_ce=sce_reg; m_ce=mce_reg; h_ce=hce_reg; clk_change s_ce=ssen; m_ce=mmen; h

19、_ce=hhen; clk_change s_ce=ssen; m_ce=secout; h_ce=minout; clk_change=clk1hz; end case; end process sel_pro; sel=ssl;s_en=ssen;m_en=mmen;h_en=hhen; end beh;6.Scan.vhdlibrary ieee;use ieee.std_logic_1164.all;entity scan isport(clk1khz : in std_logic;sl,sh,ml,mh,hl,hh : in std_logic_vector(3 downto 0);

20、clk2hz_en : in std_logic;s_ce,m_ce,h_ce : in std_logic;en_out : out std_logic_vector(7 downto 0);dataout : out std_logic_vector(3 downto 0);end scan;architecture beh of scan issignal cnt : integer range 0 to 7;signal en : std_logic_vector(7 downto 0);signal clk2hz : std_logic; signal h_ce_reg,m_ce_r

21、eg,s_ce_reg : std_logic;begin h_ce_reg = not h_ce; m_ce_reg = not m_ce; s_ce_reg = not s_ce; cnt_pro : process(clk1khz) begin if clk1khzevent and clk1khz=1 then if cnt = 7 then cnt = 0; else cnt = cnt + 1; end if; end if; end process cnt_pro; clk2hz_pro :process(clk1khz) variable c : integer range 0

22、 to 499 := 0; begin if clk1khzevent and clk1khz=1 then if clk2hz_en =1 then if c =499 then c := 0 ; clk2hz = not clk2hz; else c := c + 1; end if; else clk2hz dataout = sl;en dataout = sh;en dataout = ml;en dataout = mh;en dataout = hl;en dataout = hh;en dataout = 1010;en dataout = 1010;en null; end case; end process scan_pro; en_out = en or (clk2hz & clk2hz) or (h_ce_reg & h_ce_reg) & clk2hz & (clk2hz & clk2hz) or (m_ce_reg & m_ce_reg) & clk2hz & (clk2hz & clk2hz) or (s_ce_reg & s_ce_reg);