verilog实验37个程序.docx
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verilog实验37个程序
3-8译码器
//学习38译码器的原理,
//拨码开关的123作为输入
//本实验采用拨码开关来作为输入,LED作为状态显示
//当然如果你的学习板没有拨码开关,可以用key1key2key3作为数据输入。
//视频教程适合我们21EDA电子的所有学习板
moduledecoder_38(out,key_in);
output[7:
0]out;//38译码器输出有8钟状态,所以要8个LED灯。
input[2:
0]key_in;//(123)key1key2key3作为数据输入
reg[7:
0]out;
always@(key_in)
begin
case(key_in)
3'd0:
out=8'b11111110;//LED作为状态显示,低电平有效
3'd1:
out=8'b11111101;
3'd2:
out=8'b11111011;
3'd3:
out=8'b11110111;
3'd4:
out=8'b11101111;
3'd5:
out=8'b11011111;
3'd6:
out=8'b10111111;
3'd7:
out=8'b01111111;
endcase
end
endmodule
1位数码管动态显示
//一位数码管试验
//利用分频计数器得到数码管,效果
//视频教程适合我们21EDA电子的所有学习板
moduleSMG_LED(clk_50M,rst,led_bit,dataout);
inputclk_50M,rst;//系统时钟50M输入从12脚输入。
output[7:
0]dataout;//我们这里用数码管,
outputled_bit;//一位数码管的位选择
reg[7:
0]dataout;
regled_bit;
reg[27:
0]count;//分频计数器
//分频计数器
always@(posedgeclk_50M)
begin
count<=count+1;//计数器自加
end
always@(posedgeclk_50Mornegedgerst)
begin
led_bit<='b0;//是数码管的位选择处于导通状态
case(count[27:
24])
//case(count[27:
24])这一句希望初学者看明白,
//也是分频的关键
//在数码管上面显示0到F
0:
dataout<=8'b11000000;//0
1:
dataout<=8'b11111001;
2:
dataout<=8'b10100100;
3:
dataout<=8'b10110000;
4:
dataout<=8'b10011001;
5:
dataout<=8'b10010010;
6:
dataout<=8'b10000010;
7:
dataout<=8'b11111000;
8:
dataout<=8'b10000000;
9:
dataout<=8'b10010000;
10:
dataout<=8'b10001000;
11:
dataout<=8'b10000011;
12:
dataout<=8'b11000110;
13:
dataout<=8'b10100001;
14:
dataout<=8'b10000110;
15:
dataout<=8'b10001110;//f
endcase
end
endmodule
7段数码管静态显示
//本实验就是学习单个数码管的显示
//视频教程适合我们21EDA电子的所有学习板
moduleSMG_LED(clk_50M,led_bit,dataout);
inputclk_50M;//系统时钟50M输入从12脚输入。
output[7:
0]dataout;//我们这里用数码管,
outputled_bit;//一位数码管的位选择
reg[7:
0]dataout;
regled_bit;
always@(posedgeclk_50M)
begin
led_bit<='b0;//是数码管的位选择处于导通状态
dataout<=8'b11000000;//修改7段码,可以显示不同的字符
//本实验初始是在数码管显示0
end
endmodule
8位优先编码器
//学习编码器的原理
//优先编码器,拨码开关来作为输入,结果由数码管显示
moduleencode(a,c,en);
input[8:
1]a;//由键盘输入数据
output[7:
0]c;//结果由数码管显示
reg[7:
0]c;
output[7:
0]en;
reg[3:
0]c_tmp;
integeri;
assignen=0;
always@(a)
begin
c_tmp=0;
for(i=1;i<9;i=i+1)begin
if(a[i])
c_tmp=i;
end
end
always@(c_tmp)
begin
//下面是7段码显示的段码
case(c_tmp)
4'b0000:
c=8'b11000000;//0
4'b0001:
c=8'b11111001;//1
4'b0010:
c=8'b10100100;
4'b0011:
c=8'b10110000;
4'b0100:
c=8'b10011001;
4'b0101:
c=8'b10010010;
4'b0110:
c=8'b10000010;
4'b0111:
c=8'b11111000;
4'b1000:
c=8'b10000000;
4'b1001:
c=8'b10010000;
4'b1010:
c=8'b10001000;
4'b1011:
c=8'b10000011;
4'b1100:
c=8'b11000110;
4'b1101:
c=8'b10100001;
4'b1110:
c=8'b10000110;
4'b1111:
c=8'b10001110;//f
endcase
end
endmodule
buzzer
/*
向蜂鸣器发送一定频率的方波可以使蜂鸣器发出相应的音调,该实验通过设计一个状态机和分频
器使蜂鸣器发出"多来咪发梭拉西多"的音调。
*/
modulebuzzer(clk,rst,out);
inputclk,rst;
outputout;
regout;
reg[3:
0]clk_div1;//基频分频计数器,基频为4M
reg[12:
0]clk_div2;//音阶分频计数器,由基频分频产生各个音阶
reg[21:
0]cnt;//各音阶发声时间长短计数器
reg[2:
0]state;
parameterduo=3822,//各个音调的分频系数
lai=3405,
mi=3034,
fa=2865,
suo=2551,
la=2273,
xi=2024,
duo1=1911;
always@(posedgeclkornegedgerst)
begin
if(!
rst)begin
clk_div1<=0;
end
elsebegin
if(clk_div1!
=9)
clk_div1<=clk_div1+1;
else
clk_div1<=0;
end
end
always@(posedgeclkornegedgerst)
begin
if(!
rst)begin
clk_div2<=0;
state<=0;
cnt<=0;
out<=0;
end
elseif(clk_div1==9)begin
case(state)
3'b000:
begin//发“多”
cnt<=cnt+1;
if(cnt==22'h3fffff)
state<=3'b001;
if(clk_div2!
=duo)
clk_div2<=clk_div2+1;
elsebegin
clk_div2<=0;
out<=~out;
end
end
3'b001:
begin//发“来”
cnt<=cnt+1;
if(cnt==22'h3fffff)
state<=3'b010;
if(clk_div2!
=lai)
clk_div2<=clk_div2+1;
elsebegin
clk_div2<=0;
out<=~out;
end
end
3'b010:
begin//发"米“
cnt<=cnt+1;
if(cnt==22'h3fffff)
state<=3'b011;
if(clk_div2!
=mi)
clk_div2<=clk_div2+1;
elsebegin
clk_div2<=0;
out<=~out;
end
end
3'b011:
begin//发"法“
cnt<=cnt+1;
if(cnt==22'h3fffff)
state<=3'b100;
if(clk_div2!
=fa)
clk_div2<=clk_div2+1;
elsebegin
clk_div2<=0;
out<=~out;
end
end
3'b100:
begin//发"梭“
cnt<=cnt+1;
if(cnt==22'h3fffff)
state<=3'b101;
if(clk_div2!
=suo)
clk_div2<=clk_div2+1;
elsebegin
clk_div2<=0;
out<=~out;
end
end
3'b101:
begin//发"拉“
cnt<=cnt+1;
if(cnt==22'h3fffff)
state<=3'b110;
if(clk_div2!
=la)
clk_div2<=clk_div2+1;
elsebegin
clk_div2<=0;
out<=~out;
end
end
3'b110:
begin//发"西“
cnt<=cnt+1;
if(cnt==22'h3fffff)
state<=3'b111;
if(clk_div2!
=xi)
clk_div2<=clk_div2+1;
elsebegin
clk_div2<=0;
out<=~out;
end
end
3'b111:
begin//发"多“(高音)
cnt<=cnt+1;
if(cnt==22'h3fffff)
state<=3'b000;
if(clk_div2!
=duo1)
clk_div2<=clk_div2+1;
elsebegin
clk_div2<=0;
out<=~out;
end
end
endcase
end
end
endmodule
LCD1602_B
//
//本实验是用LCD1602显示英文。
(LCD带字库)
//视频教程适合我们21EDA电子的所有学习板
modulelcd(clk,rs,rw,en,dat);
inputclk;//系统时钟输入50M
output[7:
0]dat;//LCD的8位数据口
outputrs,rw,en;//LCD的控制脚
rege;
reg[7:
0]dat;
regrs;
reg[15:
0]counter;
reg[4:
0]current,next;
regclkr;
reg[1:
0]cnt;
parameterset0=4'h0;
parameterset1=4'h1;
parameterset2=4'h2;
parameterset3=4'h3;
parameterdat0=4'h4;
parameterdat1=4'h5;
parameterdat2=4'h6;
parameterdat3=4'h7;
parameterdat4=4'h8;
parameterdat5=4'h9;
parameterdat6=4'hA;
parameterdat7=4'hB;
parameterdat8=4'hC;
parameterdat9=4'hD;
parameterdat10=4'hE;
parameterdat11=5'h10;
parameternul=4'hF;
always@(posedgeclk)
begin
counter=counter+1;
if(counter==16'h000f)
clkr=~clkr;
end
always@(posedgeclkr)
begin
current=next;
case(current)
set0:
beginrs<=0;dat<=8'h31;next<=set1;end//*设置8位格式,2行,5*7*
set1:
beginrs<=0;dat<=8'h0C;next<=set2;end//*整体显示,关光标,不闪烁*/
set2:
beginrs<=0;dat<=8'h6;next<=set3;end//*设定输入方式,增量不移位*/
set3:
beginrs<=0;dat<=8'h1;next<=dat0;end//*清除显示*/
//上面是LCD的初始化
dat0:
beginrs<=1;dat<=8'h3C;next<=dat1;end
dat1:
beginrs<=1;dat<="F";next<=dat2;end
dat2:
beginrs<=1;dat<="P";next<=dat3;end
dat3:
beginrs<=1;dat<="G";next<=dat4;end
dat4:
beginrs<=1;dat<="A";next<=dat5;end
dat5:
beginrs<=1;dat<=8'h3E;next<=dat6;end
dat6:
beginrs<=1;dat<="G";next<=dat7;end
dat7:
beginrs<=1;dat<="O";next<=dat8;end
dat8:
beginrs<=1;dat<="O";next<=dat9;end
dat9:
beginrs<=1;dat<="D";next<=dat10;end
dat10:
beginrs<=1;dat<="!
";next<=dat11;end
dat11:
beginrs<=1;dat<="!
";next<=nul;end
//上面是在这12个状态中要显示的字符FPGAGOOD!
!
nul:
beginrs<=0;dat<=8'h00;//行一遍然后把液晶的E脚拉高
if(cnt!
=2'h2)
begin
e<=0;next<=set0;cnt<=cnt+1;
end
else
beginnext<=nul;e<=1;
end
end
default:
next=set0;
endcase
end
assignen=clkr|e;
assignrw=0;
endmodule
LCD12864显示汉字
//利用VHDL驱动LCD12864
//视频教程适合我们21EDA电子的所有学习板)
//本实验是用LCD12864显示汉字。
(LCD带字库)
moduleLCD12864(clk,rs,rw,en,dat);
inputclk;//系统时钟输入50M
output[7:
0]dat;//LCD的8位数据口
outputrs,rw,en;//LCD的控制脚
rege;
reg[7:
0]dat;
regrs;
reg[15:
0]counter;
reg[6:
0]current,next;
regclkr;
reg[1:
0]cnt;
parameterset0=6'h0;
parameterset1=6'h1;
parameterset2=6'h2;
parameterset3=6'h3;
parameterset4=6'h4;
parameterset5=6'h5;
parameterset6=6'h6;
parameterdat0=6'h7;
parameterdat1=6'h8;
parameterdat2=6'h9;
parameterdat3=6'hA;
parameterdat4=6'hB;
parameterdat5=6'hC;
parameterdat6=6'hD;
parameterdat7=6'hE;
parameterdat8=6'hF;
parameterdat9=6'h10;
parameterdat10=6'h12;
parameterdat11=6'h13;
parameterdat12=6'h14;
parameterdat13=6'h15;
parameterdat14=6'h16;
parameterdat15=6'h17;
parameterdat16=6'h18;
parameterdat17=6'h19;
parameterdat18=6'h1A;
parameterdat19=6'h1B;
parameterdat20=6'h1C;
parameterdat21=6'h1D;
parameterdat22=6'h1E;
parameterdat23=6'h1F;
parameterdat24=6'h20;
parameterdat25=6'h21;
parameterdat26=6'h22;
parameterdat27=6'h23;
parameterdat28=6'h24;
parameterdat29=6'h25;
parameterdat30=6'h26;
parameterdat31=6'h27;
parameterdat32=6'h28;
parameterdat33=6'h29;
parameterdat34=6'h2A;
parameterdat35=6'h2B;
parameterdat36=6'h2C;
parameterdat37=6'h2E;
parameterdat38=6'h2F;
parameterdat39=6'h30;
parameterdat40=6'h31;
parameterdat41=6'h32;
parameterdat42=6'h33;
parameterdat43=6'h34;
parameternul=6'h35;
always@(posedgeclk)//dadeshizhongpinlv
begin
counter=counter+1;
if(counter==16'h000f)
clkr=~clkr;
end
always@(posedgeclkr)
begin
current=next;
case(current)
set0:
beginrs<=0;dat<=8'h31;next<=set1;end//*设置8位格式,2行,5*7*
set1:
beginrs<=0;dat<=8'h0C;next<=set2;end//*整体显示,关光标,不闪烁*/
set2:
beginrs<=0;dat<=8'h6;next<=set3;end//*设定输入方式,增量不移位*/
set3:
beginrs<=0;dat<=8'h1;next<=dat0;end//*清除显示*/
dat0:
beginrs<=1;dat<=8'hc9;next<=dat1;end//显示第一行
dat1:
beginrs<=1;dat<=8'hee;next<=dat2;end
dat2:
beginrs<=1;dat<=8'hdb;next<=dat3;end
dat3:
beginrs<=1;dat<=8'hda;next<=dat4;end
dat4:
beginrs<=1;dat<=8'hca;next<=dat5;end
dat5:
beginrs<=1;dat<=8'hd0;next<=dat6;end
dat6:
beginrs<=1;dat<="2";next<=dat7;end
dat7:
beginrs<=1;dat<="1";next<=dat8;end
dat8:
beginrs<=1;dat<="E";next<=dat9;end
dat9:
beginrs<=1;dat<="D";next<=dat10;end
dat10:
beginrs<=1;dat<