LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYh_suberIS
PORT(x,y:
INSTD_LOGIC;
diff,s_out:
OUTSTD_LOGIC);
ENDENTITYh_suber;
ARCHITECTUREhs1OFh_suberIS
BEGIN
Diff<=xXOR(NOTy);
s_out<=(NOTx)ANDy;
ENDARCHITECTUREhs1;
--解(1.2):
采用例化实现图4-20的1位全减器
LIBRARYIEEE;--1位二进制全减器顺层设计描述
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYf_suberIS
PORT(xin,yin,sub_in:
INSTD_LOGIC;
sub_out,diff_out:
OUTSTD_LOGIC);
ENDENTITYf_suber;
ARCHITECTUREfs1OFf_suberIS
COMPONENTh_suber--调用半减器声明语句
PORT(x,y:
INSTD_LOGIC;
diff,s_out:
OUTSTD_LOGIC);
ENDCOMPONENT;
SIGNALa,b,c:
STD_LOGIC;--定义1个信号作为内部的连接线。
BEGIN
u1:
h_suberPORTMAP(x=>xin,y=>yin,diff=>a,s_out=>b);
u2:
h_suberPORTMAP(x=>a,y=>sub_in,diff=>diff_out,s_out=>c);
sub_out<=cORb;
ENDARCHITECTUREfs1;
(2)以1位全减器为基本硬件,构成串行借位的8位减法器,要求用例化语句来完成此项设计(减法运算是x-y-sun_in=difft)。
xinsub_out
yinu0
sub_indiff_out
x0
y0
sin
diff0
xinsub_out
yinu1
sub_indiff_out
x1
y1
diff1
xinsub_out
yinu7
sub_indiff_out
x7
y7
sout
diff7
……………….
……………….
串行借位的8位减法器
a0
a1
a6
--解
(2):
采用例化方法,以1位全减器为基本硬件;实现串行借位的8位减法器(上图所示)。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYsuber_8IS
PORT(x0,x1,x2,x3,x4,x5,x6,x7:
INSTD_LOGIC;
y0,y1,y2,y3,y4,y5,y6,y7,sin:
INSTD_LOGIC;
diff0,diff1,diff2,diff3:
OUTSTD_LOGIC;
diff4,diff5,diff6,diff7,sout:
OUTSTD_LOGIC);
ENDENTITYsuber_8;
ARCHITECTUREs8OFsuber_8IS
COMPONENTf_suber--调用全减器声明语句
PORT(xin,yin,sub_in:
INSTD_LOGIC;
sub_out,diff_out:
OUTSTD_LOGIC);
ENDCOMPONENT;
SIGNALa0,a1,a2,a3,a4,a5,a6:
STD_LOGIC;--定义1个信号作为内部的连接线。
BEGIN
u0:
f_suberPORTMAP(xin=>x0,yin=>y0,diff_out=>diff0,sub_in=>sin,sub_out=>a0);
u1:
f_suberPORTMAP(xin=>x1,yin=>y1,diff_out=>diff1,sub_in=>a0,sub_out=>a1);
u2:
f_suberPORTMAP(xin=>x2,yin=>y2,diff_out=>diff2,sub_in=>a1,sub_out=>a2);
u3:
f_suberPORTMAP(xin=>x3,yin=>y3,diff_out=>diff3,sub_in=>a2,sub_out=>a3);
u4:
f_suberPORTMAP(xin=>x4,yin=>y4,diff_out=>diff4,sub_in=>a3,sub_out=>a4);
u5:
f_suberPORTMAP(xin=>x5,yin=>y5,diff_out=>diff5,sub_in=>a4,sub_out=>a5);
u6:
f_suberPORTMAP(xin=>x6,yin=>y6,diff_out=>diff6,sub_in=>a5,sub_out=>a6);
u7:
f_suberPORTMAP(xin=>x7,yin=>y7,diff_out=>diff7,sub_in=>a6,sub_out=>sout);
ENDARCHITECTUREs8;
3-8设计一个求补码的程序,输入数据是一个有符号的8位二进制(原码)数。
--解:
5-9设计一个求补码的程序,输入数据是一个有符号的8位二进制数。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYorg_patchIS
PORT(org_data:
INSTD_LOGIC_VECTOR(7DOWNTO0);--原码输入
patch_data:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));--补码输出
ENDorg_patch;
ARCHITECTUREBHVOForg_patchIS
BEGIN
PROCESS(org_data)
BEGIN
IF(org_data(7)='0')THEN
patch_data<=org_data;--org_data>=0,补码=原码。
else
patch_data<=org_data(7)&(notorg_data(6DOWNTO0))+1;--org_data<0,补码=|原码|取反+1。
ENDIF;
ENDPROCESS;
ENDBHV;
3—10
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityaddis
port(a:
instd_logic_vector(7downto0);
b:
instd_logic_vector(7downto0);
ci:
instd_logic;
co:
outstd_logic;
count:
outstd_logic_vector(7downto0));
endadd;
architecturebhvofaddis
begin
process(a,b,ci)
variabledata:
std_logic_vector(1downto0);
variablec:
std_logic;
begin
c:
=ci;
fornin0to7loop
data:
=('0'&a(n))+('0'&b(n))+('0'&c);
count(n)<=data(0);
c:
=data
(1);
endloop;
co<=c;
endprocess;
endbhv;
3-14用循环语句设计一个7人投票表决器,及一个4位4输入最大数值检测电路。
--解:
5-7用循环语句设计一个7人投票表决器,及一个4位4输出最大数值检测电路。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYvote_7IS
PORT(DIN:
INSTD_LOGIC_VECTOR(6DOWNTO0);--7位表决输入(1:
同意,0:
不同意)
G_4:
OUTSTD_LOGIC;--超过半数指示
CNTH:
OUTSTD_LOGIC_VECTOR(2DOWNTO0));--表决结果统计数
ENDvote_7;
ARCHITECTUREBHVOFvote_7IS
BEGIN
PROCESS(DIN)
VARIABLEQ:
STD_LOGIC_VECTOR(2DOWNTO0);
BEGIN
Q:
="000";
FORnIN0TO6LOOP--n是LOOP的循环变量
IF(DIN(n)='1')THENQ:
=Q+1;ENDIF;
ENDLOOP;
CNTH<=Q;
IFQ>=4THENG_4<='1';ELSEG_4<='0';ENDIF;
ENDPROCESS;
ENDBHV;
5-7用VHDL设计一个功能类似74LS160的计数器。
--解:
3-10用VHDL设计一个功能类似74LS160(异步复位和同步使能加载、计数的十进制加法计数器)的计数器。
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEE