DCDesignCompiler综合脚本命令及参考模板Word格式.docx
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suppress_message{LINT-28LINT-32LINT-33UID-401}set
alib_library_analysis_path[get_unix_variableHOME]aliashhistory
aliasrc“report_constraint
-all_violators
TCLCommandsandConstructs
setPER2.0#Defineavariableanditsvalueecho$PER#Variablesubstitution,2.0
setMARG0.95
expr$PER*$MARG#expr:
*,/,+,-,>
<
=,<
=,>
=
setpci_ports[get_portsA]#Imbeddedcommandsetpci_ports
[get_ports“Y?
?
MZ*”]#Wildcards
echo“EffctvP=\#Softquotes,1.9
[expr$PERIOD*$MARGIN]”
echo{EffctvP=\#Hardquotes
[expr$PERIOD*$MARGIN]}#,EffctvP=[expr$PER*$MARG]#Commentline
setCOMMENTin_line;
#In-linecommentsetMY_DESIGNS{B1.v...
B26.v}#foreachloopforeachDESIGN$MY_DESIGNS{read_verilog$DESIGN
}
for{seti1}{$i<
27}{incri}{#forloop
read_verilogBLOCK_$i.v
HelpfulUNIX-likeDC-shellcommands
pwd
cd
ls
history
!
7
report
sh<
UNIX_command>
printenv
get_unix_variableARCH
Constraints
reset_design
set_max_area0
create_clock-period2
–nameMain_Clk[get_portsClk1]
create_clock
–period2.5
–waveform{23.5}[get_portsClk2]
–period3.5
–nameV_Clk;
#VIRTUALclock
set_clock_uncertainty
–setup0.14[get_clocks*]
–setup0.21
–from[get_clocksMain_Clk]
–to
[get_clocksClk2]set_clock_latency
–max0.6[get_clocksMain_Clk]
set_clock_latency–source–max0.3[get_clocksMain_Clk]
set_clock_transition0.08[get_clocksMain_Clk]set_input_delay-max0.6
-clockMain_Clk[all_inputs]set_input_delay
–max0.3
–clockClk2
–
clock_fall
–add_delay[get_ports
“BE”]
set_input_delay-max0.5-clock
–network_latency_includedV_Clk
[get_ports
“ACF”]
set_output_delay-max0.8-clock
–source_latency_includedMain_Clk
[all_outputs]
set_output_delay-max1.1-clockV_Clk[get_ports“OUT2OUT7]
set_max_capacitance1.2[all_inputs]
set_load0.080[all_outputs]
set_load[expr[load_ofslow_proc/NAND2_3/A]*4][get_portsOUT3]
set_load0.12[all_inputs]
set_input_transition0.12[remove_from_collection
[all_inputs][get_portsB]]
set_driving_cell
–lib_cellFD1
–pinQ[get_portsB]
set_operating_conditions–maxWCCOM
setauto_wire_load_selectionfalse
set_wire_load_model–name1.6MGates
set_wire_load_modeenclosed
set_wire_load_model
–name200KGates[get_designs
“SUB1SUB2”]
set_wire_load_model–name3.2MGates[get_portsIN_A]set_port_fanout_number8[get_portsIN_A]set_false_path-from[get_clocksAsynch_CLKA]-to[get_clocksAsynch_CLKB]
set_multicycle_path–setup4–from–fromA_reg-through
U_Mult/Out–toB_reg
set_multicycle_path–hold3–from–fromA_reg-through
set_isolate_ports–typeinverter[all_outputs]
set_ideal_network[get_portsreset*select*]set_ideal_network
[get_pinsFF_SET_reg/Q]set_ideal_network–no_propagate[get_netsCTRL]
set_ideal_latency1.4[get_portsreset*select*]
set_ideal_transition0.5[get_pinsFF_SET_reg/Q]set_scan_configuration
-style<
multiplexed_flip_flop|clocked_scan|lssd|aux_clock_lssd>
CheckingandRemovingConstraintsandDirectivesreport_clock;
report_clock-skew
report_design
report_port–verbose
report_wire_load
report_path_groups
report_timing_requirements（
–ignored）report_auto_ungroup
report_isolate_portswrite_scriptcheck_timing
–output<
constraints.tcl>
reset_path–fromFF1_reg
remove_clock
remove_clock_transitionremove_clock_uncertaintyremove_input_delayremove_output_delayremove_driving_cellremove_wire_load_modelSyntaxChecking
Unix%dcprocheckconstr_file.con
PhysicalConstraints–TopographicalMode
set_aspect_ratio
set_utilization
set_placement_area
set_rectilinear_outlineset_port_side
set_port_location
set_cell_location
create_placement_keepout
Misc.Reports
#GenerateAlibraryreportfile
read_dblibrary_file.db
list_libs
redirect–filereports/lib.rpt{report_lib<
libname>
report_hierarchy[-noleaf]
#Arithmeticimplementationand
#resource-sharinginforeport_resources
#Listareaforallcellsinthedesignreport_cell[get_cells
hier*]
RunScript
read_verilog{A.vB.vTOP.v}or
read_vhdl{A.vhdB.vhdTOP.vhd}or
read_ddcMY_TOP.ddcor
acs_read_hdlMY_TOPor
analyze
–formatverilog{A.vB.vTOP.v}
elaborateMY_TOP
–parameters
“A_WIDTH=8,B_WIDTH=16”
current_designMY_TOP
link
if{[check_design]==0}{
echo“CheckDesignError”
exit#ExitsDCifacheck-designerrorisencountered}#ContinueifNOproblemsencountered
write–fddc–hier–outunmappedd/TOP.ddc
redirect–tee–filereports/precompile.rpt{source–echo-verbose
TOP.con}redirect–append–tee–filereports/precompile.rpt{check_timing}source<
Physical_Constraints_TCL_file>
or#Sourcetclconstraints,ifavailable,or
extract_physical_constraints<
DEF_file>
#Extractandapplyfromanexisting
#DEFfloorplanfile
group_path-nameCLK1-critical_range<
10%ofCLK1Period>
–weight
5
group_path-nameCLK2-critical_range<
10%ofCLK2Period>
2
group_path
–nameINPUTS–from[all_inputs]
–nameOUTPUTS–to[all_outputs]
–nameCOMBO–from[all_inputs]
–to[all_outputs]
set_fix_multiple_port_nets–all–buffer_constants
***********************************************************
*InsertExpert,UltraorACScompileflowhere***
*********************************************************
check_design
report_constraint–all_violators
report_timing–delay–to–from–through–input_pins–max_paths
\
–nworst–nets–cap–sig–groupreport_area
report_qor
setverilogout_no_tritrue
change_names–ruleverilog
–hier
write
–fverilog
–outmapped/TOP.v
write–fddc–hier–outmapped/TOP.ddc
write_sdcTOP.sdc
write_scan_def–outTOP_scan.def
write_physical_constraints–outputTOP_PhysConstr.tclexit
ObjectRetrievalandManipulation（CollectionCommands）
get_ports,get_pins,get_designs
get_cells,get_nets,get_clocks
get_nets–of_objects[get_pinsFF1_reg/Q]get_libs<
lib_name>
get_lib_cells<
lib_name/cell_names>
get_lib_pins
<
lib_name/cell_name/pin_names>
all_inputs,all_outputs,all_clocks,all_registersall_connected
all_fanin,all_fanout
all_ideal_nets
setpci_ports[get_portspci_*]
echo$pci_ports#,_sel184
query_objects$pci_ports#,{pci_1pci_2...}get_object_name
$pci_ports#,pci_1pci_2...
sizeof_collection$pci_ports#,37
setpci_ports[add_to_collection$pci_ports\
[get_portsCTRL*]]
setall_inputs_except_clk[remove_from_collection\
[all_inputs][get_portsCLK]]
compare_collections
index_collection
sort_collection
foreach_in_collectionmy_cells[get_cells-hier*\
-filter
“is_hierarchical==true
”]{
echo
“Instance[get_object_name$cell]ishierarchical
#Filteringoperators:
==,!
>
=,<
=,=~,!
~
filter_collection[get_cells*]
“ref_name=~AN*”
get_cells*-
filter
“dont_touch==true
get_clocks*-filter“period<
10”
#Listallcellattributesandredirectoutputtoafileredirect–filecell_attr\
{list_attributes–application–classcell}
#Grepthefileforcellattributesstartingwithdont_
UNIX%grepdont_cell_attr|more
#Listthevalueoftheattributedont_touchget_attribute<
cell_name>
dont_touch
UltraCompileFlow-TopographicalorWLMModeUltra+DesignWareandDFTClicensesavailable
#In
“topo”
mode（dc_shell
-t
–topo）specifyMilkywayreference
anddesignlibrariescreate_mw_lib–tech<
technology_file>
-
mw_reference_library<
mw_reference_libraries>
\
mw_design_library_name>
open_mw_lib<
set_tlu_plus_files-max_tluplus<
max_tluplus_file>
-tech2itf_map<
mapping_file>
setcompile_auto_ungroup_delay_num_cells99999999
setcompile_auto_ungroup_count_leaf_cellstrue
setcompile_auto_ungroup_override_wlmtrue
set_ungroup<
top_level_and/or_pipelined_blocks>
false
#OPTIONAL:
Disableunconditionalauto-ungrouping
#ofDesignWarehierarchy（notusuallyrecommended）setcompile_ultra_ungroup_dwfalse
#Ifdesigncontainspipelinedsub-designsandthepipelineregisters
#aregroupedtogetherattheinputoroutput,relaxtiming
set_multicycle_path
–setup<
#_stages>
-fromU_Pipeline/R3_reg*
U_Pipeline/R7_
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