DCDesignCompiler综合脚本命令及参考模板Word格式.docx

1、suppress_message LINT-28 LINT-32 LINT-33 UID-401 setalib_library_analysis_path get_unix_variable HOME alias h historyalias rc “report_constraint- all_violatorsTCL Commands and Constructsset PER 2.0 # Define a variable and its value echo $PER # Variable substitution , 2.0set MARG 0.95expr $PER * $MAR

2、G # expr: *, /, +, -, , , =, =set pci_ports get_ports A # Imbedded command set pci_portsget_ports “Y?M Z*” # Wildcardsecho “Effctv P = # Soft quotes , 1.9expr $PERIOD * $MARGIN ”echo Effctv P = # Hard quotesexpr $PERIOD * $MARGIN # , Effctv P = expr $PER * $MARG # Comment lineset COMMENT in_line; #

3、In-line comment set MY_DESIGNS B1.v .B26.v # foreach loop foreach DESIGN $MY_DESIGNS read_verilog $DESIGNfor set i 1 $i 27 incr i # for loopread_verilog BLOCK_$i.vHelpful UNIX-like DC-shell commandspwdcdlshistory!7reportsh printenvget_unix_variable ARCHConstraintsreset_designset_max_area 0create_clo

4、ck -period 2 name Main_Clk get_ports Clk1create_clockperiod 2.5 waveform 2 3.5 get_ports Clk2period 3.5 name V_Clk; # VIRTUAL clockset_clock_uncertaintysetup 0.14 get_clocks *setup 0.21 from get_clocks Main_Clk toget_clocks Clk2 set_clock_latencymax 0.6 get_clocks Main_Clkset_clock_latency source ma

5、x 0.3 get_clocks Main_Clkset_clock_transition 0.08 get_clocks Main_Clk set_input_delay -max 0.6-clock Main_Clk all_inputs set_input_delaymax 0.3 clock Clk2clock_falladd_delay get_ports“B E”set_input_delay -max 0.5 -clock network_latency_included V_Clkget_ports“A C F”set_output_delay -max 0.8 -clocks

6、ource_latency_included Main_Clkall_outputsset_output_delay -max 1.1 - clock V_Clk get_ports “OUT2 OUT7set_max_capacitance 1.2 all_inputsset_load 0.080 all_outputsset_load expr load_of slow_proc/NAND2_3/A * 4 get_ports OUT3set_load 0.12 all_inputsset_input_transition 0.12 remove_from_collectionall_in

7、putsget_ports Bset_driving_celllib_cell FD1 pin Q get_ports Bset_operating_conditions max WCCOMset auto_wire_load_selection falseset_wire_load_model name 1.6MGatesset_wire_load_mode enclosedset_wire_load_modelname 200KGates get_designs“SUB1 SUB2”set_wire_load_model name 3.2MGates get_ports IN_A set_

8、port_fanout_number 8 get_ports IN_A set_false_path -from get_clocks Asynch_CLKA -to get_clocks Asynch_CLKBset_multicycle_path setup 4 from from A_reg -throughU_Mult/Out to B_regset_multicycle_path hold 3 from from A_reg -throughset_isolate_ports type inverter all_outputsset_ideal_network get_ports r

9、eset* select* set_ideal_networkget_pins FF_SET_reg/Q set_ideal_network no_propagate get_nets CTRLset_ideal_latency 1.4 get_ports reset* select*set_ideal_transition 0.5 get_pins FF_SET_reg/Q set_scan_configuration-style Checking and Removing Constraints and Directives report_clock; report_clock -skew

10、report_designreport_port verbosereport_wire_loadreport_path_groupsreport_timing_requirements （ignored） report_auto_ungroupreport_isolate_ports write_script check_timingoutput reset_path from FF1_regremove_clockremove_clock_transition remove_clock_uncertainty remove_input_delay remove_output_delay re

11、move_driving_cell remove_wire_load_model Syntax CheckingUnix% dcprocheck constr_file.conPhysical Constraints Topographical Modeset_aspect_ratioset_utilizationset_placement_areaset_rectilinear_outline set_port_sideset_port_locationset_cell_locationcreate_placement_keepoutMisc. Reports# Generate A lib

12、rary report fileread_db library_file.dblist_libsredirect file reports/lib.rpt report_lib report_hierarchy -noleaf# Arithmetic implementation and# resource-sharing info report_resources# List area for all cells in the design report_cell get_cellshier *Run Scriptread_verilog A.v B.v TOP.v orread_vhdl

13、A.vhd B.vhd TOP.vhd orread_ddc MY_TOP.ddc oracs_read_hdl MY_TOP oranalyzeformat verilog A.v B.v TOP.velaborate MY_TOPparameters“A_WIDTH=8, B_WIDTH=16”current_design MY_TOPlinkif check_design =0 echo “Check Design Error ”exit # Exits DC if a check-design error is encountered # Continue if NO problems

14、 encounteredwrite f ddc hier out unmappedd/TOP.ddcredirect tee file reports/precompile.rpt source echo -verboseTOP.con redirect append tee file reports/precompile.rpt check_timing source or # Source tcl constraints, if available, orextract_physical_constraints # Extract and apply from an existing# D

15、EF floorplan filegroup_path -name CLK1 -critical_range weight5group_path -name CLK2 -critical_range 2group_pathname INPUTSfrom all_inputsname OUTPUTS to all_outputsname COMBOfrom all_inputs to all_outputsset_fix_multiple_port_nets all buffer_constants* * * Insert Expert, Ultra or ACS compile flow he

16、re * * *check_designreport_constraint all_violatorsreport_timing delay to from through input_pins max_paths nworst nets cap sig group report_areareport_qorset verilogout_no_tri truechange_names rule veriloghierwrite f verilogout mapped/TOP.vwrite f ddc hier out mapped/TOP.ddcwrite_sdc TOP.sdcwrite_s

17、can_def out TOP_scan.defwrite_physical_constraints output TOP_PhysConstr.tcl exitObject Retrieval and Manipulation （Collection Commands）get_ports, get_pins, get_designsget_cells, get_nets, get_clocksget_nets of_objects get_pins FF1_reg/Q get_libs get_lib_cells get_lib_pins all_inputs, all_outputs, a

18、ll_clocks, all_registers all_connectedall_fanin, all_fanoutall_ideal_netsset pci_ports get_ports pci_*echo $pci_ports # , _sel184query_objects $pci_ports # , pci_1 pci_2 . get_object_name$pci_ports # , pci_1 pci_2 .sizeof_collection $pci_ports # , 37set pci_ports add_to_collection $pci_ports get_por

19、ts CTRL*set all_inputs_except_clk remove_from_collection all_inputs get_ports CLKcompare_collectionsindex_collectionsort_collectionforeach_in_collection my_cells get_cells -hier * - filter“is_hierarchical = true” echo“Instance get_object_name $cell is hierarchical# Filtering operators: =, !, =, =, =

20、, !filter_collection get_cells *“ref_name = AN* ”get_cells * -filter“dont_touch = trueget_clocks * - filter “period 10 ”#List all cell attributes and redirect output to a file redirect file cell_attr list_attributes application class cell# Grep the file for cell attributes starting with dont_UNIX% g

21、rep dont_ cell_attr | more#List the value of the attribute dont_touch get_attribute dont_touchUltra Compile Flow - Topographical or WLM Mode Ultra + DesignWare and DFTC licenses available# In“topo ”mode （dc_shell-ttopo） specify Milkyway referenceand design libraries create_mw_lib tech -mw_reference_

22、library mw_design_library_nameopen_mw_lib set_tlu_plus_files -max_tluplus -tech2itf_map set compile_auto_ungroup_delay_num_cells 99999999set compile_auto_ungroup_count_leaf_cells trueset compile_auto_ungroup_override_wlm trueset_ungroup false#OPTIONAL: Disable unconditional auto-ungrouping#of DesignWare hierarchy （not usually recommended） set compile_ultra_ungroup_dw false#If design contains pipelined sub-designs and the pipeline registers#are grouped together at the input or output, relax timingset_multicycle_path setup -from U_Pipeline/R3_reg*U_Pipeline/R7_