VHDL流水线加法器Word格式.docx
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libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
useieee.std_logic_arith.all;
entityadderis
port(
clk,rst:
instd_logic;
a,b:
instd_logic_vector(3downto0);
sum:
outstd_logic_vector(3downto0);
c:
outstd_logic);
endentityadder;
architecturedepictofadderis
signalreg1:
std_logic_vector(7downto0);
signalreg2:
std_logic_vector(6downto0);
signalreg3:
std_logic_vector(5downto0);
begin
bit0:
process(clk,rst)
begin
if(rst='
1'
)then
reg1<
="
00000000"
elsif(rising_edge(clk))then
reg1(0)<
=a(0)xorb(0);
reg1
(1)<
=a(0)andb(0);
reg1
(2)<
=a
(1);
reg1(3)<
=b
(1);
reg1(4)<
=a
(2);
reg1(5)<
=b
(2);
reg1(6)<
=a(3);
reg1(7)<
=b(3);
endif;
endprocessbit0;
bit1:
reg2<
0000000"
reg2(0)<
=reg1(0);
reg2
(1)<
=reg1
(1)xorreg1
(2)xorreg1(3);
reg2
(2)<
=(reg1
(1)andreg1
(2))or(reg1
(1)andreg1(3))or(reg1
(2)andreg1(3));
reg2(6downto3)<
=reg1(7downto4);
endprocessbit1;
bit2:
reg3<
000000"
reg3(1downto0)<
=reg2(1downto0);
reg3
(2)<
=reg2
(2)xorreg2(3)xorreg2(4);
reg3(3)<
=(reg2
(2)andreg2(3))or(reg2
(2)andreg2(4))or(reg2(3)andreg2(4));
reg3(5downto4)<
=reg2(6downto5);
endprocessbit2;
bit3:
sum<
0000"
c<
='
0'
sum(2downto0)<
=reg3(2downto0);
sum(3)<
=reg3(3)xorreg3(4)xorreg3(5);
=(reg3(3)andreg3(4))or(reg3(3)andreg3(5))or(reg3(4)andreg3(5));
endprocessbit3;
enddepict;
entitynoaddis
endentitynoadd;
architecturedepictofnoaddis
signalreg:
std_logic_vector(4downto0);
signalrega:
signalregb:
process(clk)
begin
if(rising_edge(clk))then
rega<
&
a;
regb<
b;
endif;
endprocess;
if(rst='
)then
reg<
00000"
elsif(rising_edge(clk))then
=rega+regb;
endif;
sum<
=reg(3downto0);
c<
=reg(4);
4位十进制数计数器
entitydec_dispisport(
clk_cnt:
sel1:
sel2:
sel3:
sel4:
outstd_logic_vector(3downto0));
enddec_disp;
architecturebehavofdec_dispis
signaldata1:
std_logic_vector(3downto0);
signaldata2:
signaldata3:
signaldata4:
count:
process(clk_cnt)
if(rising_edge(clk_cnt))then
if(data1="
1001"
data1<
if(data2="
data2<
=data1+1;
if(data3="
data3<
=data2+1;
if(data4="
data4<
=data3+1;
=data4+1;
endif;
endprocesscount;
sel1<
=data1;
sel2<
=data2;
sel3<
=data3;
sel4<
=data4;
endbehav;
正弦波发生器
sin.mif文件
depth=256;
width=8;
address_radix=dec;
data_radix=dec;
content
0:
131;
1:
134;
2:
137;
3:
141;
4:
144;
5:
147;
6:
150;
7:
153;
8:
156;
9:
159;
10:
162;
11:
165;
12:
168;
13:
171;
14:
174;
15:
177;
16:
180;
17:
183;
18:
186;
19:
188;
20:
191;
21:
194;
22:
196;
23:
199;
24:
202;
25:
204;
26:
207;
27:
209;
28:
212;
29:
214;
30:
216;
31!
219;
32:
221;
33:
223;
34:
225;
35:
227;
36:
229;
37:
231;
38:
233;
39:
234;
40:
236;
41:
238;
42:
239;
43:
241;
44:
242;
45:
244;
46:
245;
47:
246;
48:
247;
49:
249;
50:
250;
51:
52:
251;
53:
252;
54:
253;
55:
254;
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57:
255;
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91:
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95:
96:
216;
97:
214;
98:
212;
99:
209;
100:
207;
101:
204;
102:
202;
103:
199;
104:
196;
105:
194;
106:
191;
107:
188;
108:
186;
109:
183;
110:
180;
111:
177;
112:
174;
113:
171;
114:
168;
115:
165;
116:
162;
117:
159;
118:
156;
119:
153;
120:
150;
121:
147;
122:
144;
123:
141;
124:
137;
125:
134;
126:
131;
127:
128;
128:
125;
129:
122;
130:
119;
131:
115;
132:
112;
133:
109;
134:
106;
135:
103;
136:
10;
137:
97;
138:
94;
139:
91;
140:
88;
141:
85;
142:
82;
143:
79;
144:
76;
145:
73;
146:
70;
147:
68;
148:
65;
149:
62;
150:
60;
151:
57;
152:
54;
153:
52;
154:
49;
155:
47;
156:
44;
157:
42;
158:
40;
159:
37;
160:
35;
161:
33;
162:
31;
163:
29;
164:
27;
165:
25;
166:
23;
167:
22;
168:
20;
169:
18;
170:
17;
171:
15;
172:
14;
173:
12;
174:
11;
175:
176:
9;
177:
7;
178:
6;
179:
180:
5;
181:
4;
182:
3;
183:
2;
184:
185:
1;
186:
187:
188:
0;
189:
190:
191:
192:
193:
194:
195:
196:
197:
198:
199:
200:
201:
202:
203:
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221:
222:
223:
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225:
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227:
228:
229:
230:
231:
232:
233:
234:
235:
236:
70;
237:
238:
239:
240:
241:
242:
243:
244:
245:
246:
100;
247:
248:
249:
250:
251:
252:
253:
254:
255:
end;