基于VHDL语言的EDA实验报告Word格式文档下载.docx

基于VHDL语言的EDA实验报告Word格式文档下载.docx

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ELSIFCLK'

EVENTANDCLK='

1'

THEN

IFEN='

IF（LOAD='

）THENQ:

=DATA;

ELSE

IFQ<

9THENQ:

=Q+1;

ELSEQ:

ENDIF;

IFQ="

1001"

THENCOUT<

='

;

ELSECOUT<

ENDIF;

DOUT<

=Q;

ENDPROCESS;

ENDbehav;

仿真波形：

封装图：

3-8译码器

ENTITYYM38IS

PORT（A:

INSTD_LOGIC_VECTOR（2DOWNTO0）;

EN:

Y:

OUTSTD_LOGIC_VECTOR（7DOWNTO0））;

ENDYM38;

ARCHITECTUREBEHAVOFYM38IS

SIGNALCLK:

STD_LOGIC_VECTOR（3DOWNTO0）;

CLK<

=A&

EN;

PROCESS（CLK）

CASECLKIS

WHEN"

0001"

=>

Y<

="

00000001"

0011"

00000010"

0101"

00000100"

0111"

00001000"

00010000"

1011"

00100000"

1101"

01000000"

1111"

10000000"

WHENOTHERS=>

00000000"

ENDCASE;

ENDBEHAV;

MEALY型有限状态机

实验源码:

ENTITYMEALY1IS

PORT（CLK,DIN1,DIN2,RST:

INSTDD_LOGIC;

Q:

OUTSTD_LOGIC_VECTOR（4DOWNTO0））;

ENDMEALY1;

ARCHITECTUREBEHAVOFMEALY1IS

TYPESTATESIS（ST0,ST1,ST2,ST3,ST4）;

SIGNALPST:

STATES;

REGCOM:

PROCESS（CLK,RST,PST,DIN1）BEGIN

IFRST='

THENPST<

=ST0;

ELSIFRISING_EDGE（CLK）THEN

CASEPSTIS

WHENST0=>

IFDIN1='

THENPST<

=ST1;

ELSEPST<

=ST0;

ENDIF;

WHENST1=>

=ST2;

WHENST2=>

=ST3;

WHENST3=>

=ST4;

WHENST4=>

WHENOTHERS=>

PST<

ENDPROCESSREGCOM:

COM:

PROCESS（PST,DIN2）BEGIN

CASEPSTIS

IFDIN2='

THENQ<

10000"

;

ELSEQ<

01010"

10111"

10100"

10101"

10011"

11011"

01001"

11101"

01101"

WHENOTHERS=>

Q<

00000"

ENDCASE;

ENDPROCESSCOM;

END;

跑马灯

Libraryieee;

useieee.std_logic_1164.all;

entitycyc_ledis

port（clr,clk:

instd_logic;

led1,led2,led3:

outstd_logic）;

end;

architectureaofcyc_ledis

typestatesis（s0,s1,s2,s3,s4,s5）;

signalq:

std_logic_vector（0to2）;

signalstate:

states;

begin

p1:

process（clk,clr）

begin

if（clr='

）then

state<

=s0;

led1<

led2<

led3<

elsif（clk'

eventandclk='

casestateis

whens0=>

=s1;

led2<

led3<

whens1=>

=s2;

whens2=>

=s3;

whens3=>

=s4;

whens4=>

=s5;

whens5=>

endcase;

endif;

endprocess;

实验图：

LED数码管循环显示0～9

USEIEEE.std_logic_1164.all;

USEIEEE.std_logic_arith.all;

USEIEEE.std_logic_unsigned.all;

ENTITYxianshiIS

PORT（clk:

Led7s:

outstd_logic_vector（6downto0））;

--sel:

outstd_logic_vector（1downto0））;

ENDENTITY;

ARCHITECTUREfuncOFxianshiIS

SIGNALfp,tmp:

std_logic;

SIGNALcount:

std_logic_vector（9downto0）;

SIGNALsl:

std_logic_vector（3downto0）;

--sl1:

std_logic_vector（1downto0）;

BEGIN

PROCESS（clk）

BEGIN

IF（clk'

EVENTANDclk='

）THEN

IF（count="

1111100111"

count<

=（OTHERS=>

'

tmp<

=NOTtmp;

ELSE

=count+1;

ENDIF;

ENDIF;

fp<

=tmp;

counter1:

PROCESS（fp）

IF（fp'

EVENTANDfp='

IF（sl="

）THENsl<

="

0000"

ELSEsl<

=sl+1;

diplay:

PROCESS（sl）

CASEslIS

when"

led7s<

0111111"

when"

0000110"

0010"

1011011"

1001111"

0100"

1100110"

1101101"

0110"

1111101"

0000111"

1000"

1111111"

1101111"

NULL;

ENDCASE;

ENDARCHITECTURE;

16*16点阵显示_北京欢迎

libraryieee;

useieee.std_logic_unsigned.all;

entitytest_led1is

port（clk:

dotout:

outstd_logic_vector（15downto0）;

--行驱动信号输出

selout:

outstd_logic_vector（3downto0））;

--列选信号号输出

endtest_led1;

architecturebehaveoftest_led1is

signalcount:

std_logic_vector（11downto0）;

signalq:

std_logic_vector（10downto0）;

signalcnt16:

signaldout:

std_logic_vector（15downto0）;

signala:

integerrange0to15;

signaltmp:

std_logic_vector（1downto0）:

00"

reg:

PROCESS（clk）

111110100000"

if（tmp="

11"

）thentmp<

elsetmp<

=tmp+1;

endif;

ENDPROCESS;

process（cnt16）

begin

iftmp="

then

casecnt16is

when"

=>

dout<

0010000000000000"

a<

=0;

0011000000100000"

=1;

0001100000100000"

=2;

0000100000100000"

=3;

0000010000100000"

=4;

0111111111111111"

=5;

0000000000000000"

=6;

=7;

--北

=8;

0011111111111111"

=9;

1010"

0100000001000000"

=10;

0100000000100000"

=11;

1100"

0100000000011000"

=12;

0100000000001100"

=13;

1110"

0111100000001000"

=14;

=15;

whenothers=>

null;

elsiftmp="

01"

casecnt16is

0000000000000100"

0010000000000100"

0001000000000100"

0000100111110100"

0000000100010101"

1100000100010101"

--京

1111110100010101"

0000000100010100"

10"

then

0000001000011000"

0000000100101000"

0000000001001000"

0000000010011000"

0000100100000100"

0000001000000011"

--欢

0000000010000010"

0000000000100010"

0000000000001010"

0000000001000010"

0000000100001010"

0000001000000110"

1000000000010010"

0111111111110100"

0100000000000000"

1000111111111100"

1000100000000010"

1000110000000010"

1000000000000000"

--迎

1001111111111110"

1000000000000010"

1000100001000010"

1000111111110010"

dotout<

=dout;

endprocessp1;

p2:

process（clk）

ifclk'

thenq<

=q+1;

endif;

cnt16<

=q（3downto0）;

endprocessp2;

p3:

process（a）--4/16译码电路

caseais

when0=>

selout<

when1=>

when2=>

when3=>

when4=>

when5=>

when6=>

when7=>

when8=>

when9=>

when10=>

when11=>

when12=>

when13=>

when14=>

when15=>

whenothers=>

null;

endprocessp3;

endbehave;

16*16点阵显示_河南农大

entitytest