基于VHDL语言的EDA实验报告Word格式文档下载.docx

1、 ELSIF CLKEVENT AND CLK=1 THEN IF EN= IF （LOAD=） THEN Q:=DATA;ELSE IF Q9 THEN Q:=Q+1; ELSE Q: END IF; IF Q=1001 THEN COUT=; ELSE COUTEND IF; DOUT=Q; END PROCESS;END behav;仿真波形：封装图：3-8译码器ENTITY YM38 IS PORT （A:IN STD_LOGIC_VECTOR（2 DOWNTO 0）; EN: Y:OUT STD_LOGIC_VECTOR（7 DOWNTO 0） ）;END YM38;ARCHITEC

2、TURE BEHAV OF YM38 ISSIGNAL CLK: STD_LOGIC_VECTOR（3 DOWNTO 0）;CLK Y00000000 END CASE; END BEHAV;MEALY型有限状态机实验源码:ENTITY MEALY1 ISPORT（CLK,DIN1,DIN2,RST : IN STDD_LOGIC; Q : OUT STD_LOGIC_VECTOR（4 DOWNTO 0）;END MEALY1;ARCHITECTURE BEHAV OF MEALY1 ISTYPE STATES IS （ST0, ST1, ST2, ST3,ST4）;SIGNAL PST :S

3、TATES ;REGCOM: PROCESS（CLK,RST,PST,DIN1） BEGINIF RST= THEN PST IF DIN1= THEN PST=ST1 ; ELSE PST=ST2 ; WHEN ST2=ST3 ; WHEN ST3=ST4 ; WHEN ST4= WHEN OTHERS = PST END PROCESS REGCOM:COM: PROCESS（PST,DIN2） BEGIN CASE PST IS IF DIN2= THEN Q10000 ; ELSE Q Q00000END CASE ;END PROCESS COM ;END;跑马灯Library ie

4、ee;use ieee.std_logic_1164.all;entity cyc_led is port（ clr,clk:in std_logic; led1,led2,led3:out std_logic）;end;architecture a of cyc_led is type states is（s0,s1,s2,s3,s4,s5）;signal q:std_logic_vector（0 to 2）;signal state: states;begin p1:process（clk,clr） beginif （clr=） then state=s0; led1 led2 led3=

5、s1;led2led3=s2; when s2=s3; when s3=s4; when s4=s5; when s5= end case;end if;end process;实验图：LED数码管循环显示09USE IEEE.std_logic_1164.all;USE IEEE.std_logic_arith.all;USE IEEE.std_logic_unsigned.all;ENTITY xianshi IS PORT（clk: Led7s:out std_logic_vector（6 downto 0）; -sel:out std_logic_vector（1 downto 0）;

6、END ENTITY ;ARCHITECTURE func OF xianshi ISSIGNAL fp,tmp:std_logic; SIGNAL count:std_logic_vector（9 downto 0）; SIGNAL sl:std_logic_vector（3 downto 0）; -sl1:std_logic_vector（1 downto 0）; BEGIN PROCESS（clk） BEGIN IF（clkEVENT AND clk = ） THEN IF（count = 1111100111 count tmp = NOT tmp; ELSE= count + 1;

7、END IF; END IF; fp = tmp; counter1:PROCESS（fp） IF（fpEVENT AND fp = IF（sl = ） THEN sl = 0000 ELSE sl = sl + 1; diplay:PROCESS（sl） CASE sl IS when led7s0111111 when 0000110001010110111001111010011001101101101011011111010000111100011111111101111 NULL; END CASE;END ARCHITECTURE;16*16点阵显示_北京欢迎library iee

8、e;use ieee.std_logic_unsigned.all;entity test_led1 is port（clk: dotout:out std_logic_vector（15 downto 0）;-行驱动信号输出 selout:out std_logic_vector（3 downto 0）;-列选信号号输出 end test_led1;architecture behave of test_led1 is signal count:std_logic_vector（11 downto 0）; signal q:std_logic_vector（10 downto 0）; sig

9、nal cnt16: signal dout:std_logic_vector（15 downto 0）; signal a:integer range 0 to 15; signal tmp:std_logic_vector（1 downto 0）:00reg:PROCESS（clk）111110100000 if （tmp=11）then tmp else tmp dout0010000000000000 anull;elsif tmp=01case cnt16 is00000000000001000010000000000100000100000000010000001001111101

10、0000000001000101011100000100010101 -京1111110100010101000000010001010010then000000100001100000000001001010000000000001001000000000001001100000001001000001000000001000000011 -欢000000001000001000000000001000100000000000001010000000000100001000000001000010100000001000000110100000000001001001111111111101

11、0001000000000000001000111111111100100010000000001010001100000000101000000000000000 -迎1001111111111110100000000000001010001000010000101000111111110010 dotout=dout;end process p1;p2: process（clk） if clk then q=q+1; end if; cnt16 selout when 2 = when 3 = when 4 = when 5 = when 6 = when 7 = when 8 = when 9 = when 10 = when 11 = when 12 = when 13 = when 14 = when 15 = when others = null;end process p3;end behave;16*16点阵显示_河南农大entity test