硬件结构设计Word文档下载推荐.docx

硬件结构设计Word文档下载推荐.docx

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LOC=M13;

#AtlysLD4

atlys_led[5]"

LOC=D4;

#AtlysLD5

atlys_led[6]"

LOC=P16;

#AtlysLD6

atlys_led[7]"

LOC=N12;

#AtlysLD7

###-----------AtlysSwitchinput-------------------

atlys_sw[0]"

LOC=A10;

#Atlyssw0

atlys_sw[1]"

LOC=D14;

#Atlyssw1

atlys_sw[2]"

LOC=C14;

#Atlyssw2

atlys_sw[3]"

LOC=P15;

#Atlyssw3

atlys_sw[4]"

LOC=P12;

#Atlyssw4

atlys_sw[5]"

LOC=R5;

#Atlyssw5

atlys_sw[6]"

LOC=T5;

#Atlyssw6

atlys_sw[7]"

LOC=E4;

#Atlyssw7

###------------EES261switchinput----------

din[0]"

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din[1]"

R10"

#SW19

din[2]"

U10"

#SW18

din[3]"

R8"

#SW17

S[0]"

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#SW16

S[1]"

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#SW15

S[2]"

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#SW14

S[3]"

N7"

#SW13

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swt[8]"

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swt[7]"

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#SW8

swt[6]"

P7"

#SW7

swt[5]"

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#SW6

swt[4]"

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P8"

#SW4

s1"

V7"

#SW3

s2"

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##----------EES261ledsoutput------------

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U16"

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1>

U15"

#LED2

2>

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#LED3

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#LED5

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#LED6

6>

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#LED7

7>

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###-------hex7seg-------------------

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###--------------END---------

微程序控制操作方法：

s0s1s2s3oenwe1we2gwe1oen_n1gwe2oen_n2gwe3oen_n3

0000100010101

0001010010101

0011010110101

0010010011001

0110010000001

0100000010101

0101001010101

0111001010111

1000001010110

微程序：

Romc改编代码

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useieee.std_logic_unsigned.all;

entityromcis

Port（s0:

inSTD_LOGIC;

s1:

s2:

s3:

oen:

outSTD_LOGIC;

we1:

we2:

gwe1:

oen_n1:

gwe2:

oen_n2:

gwe3:

oen_n3:

outSTD_LOGIC

）;

endromc;

architectureBehavioralofromcis

signaladdr:

std_logic_vector（1downto0）;

--input

signalrdata:

std_logic_vector（3downto0）;

--output

begin

addr<

=s3&

s2&

s1&

s0;

process（addr）

begin

case（addr）is

when"

0000"

=>

rdata<

="

100010101"

0001"

010010101"

0011"

010110101"

0010"

010011001"

0110"

010000001"

0100"

000010101"

0101"

001010101"

0111"

001010111"

1000"

001010110"

whenothers=>

000000000"

endcase;

endprocess;

oen<

=rdata（0）;

we1<

=rdata

（1）;

we2<

=rdata

（2）;

gwe1<

=rdata（3）;

oen_n1<

=rdata（4）;

gwe2<

=rdata（5）;

oen_n2<

=rdata（6）;

gwe3<

=rdata（7）;

oen_n3<

=rdata（8）;

endBehavioral;

data_bus改编代码

----------------------------------------------------------------------------------

--Company:

--Engineer:

--

--CreateDate:

16:

56:

3203/08/2013

--DesignName:

--ModuleName:

data_bus-Behavioral

--ProjectName:

--TargetDevices:

--Toolversions:

--Description:

--

--Dependencies:

--Revision:

--Revision0.01-FileCreated

--AdditionalComments:

useIEEE.STD_LOGIC_1164.ALL;

--Uncommentthefollowinglibrarydeclarationifusing

--arithmeticfunctionswithSignedorUnsignedvalues

--useIEEE.NUMERIC_STD.ALL;

--Uncommentthefollowinglibrarydeclarationifinstantiating

--anyXilinxprimitivesinthiscode.

--libraryUNISIM;

--useUNISIM.VComponents.all;

entitydata_busis

Port（clk:

data_in1:

inSTD_LOGIC_VECTOR（3downto0）;

data_in2:

data_in3:

data_in4:

data_out1:

outSTD_LOGIC_VECTOR（3downto0）;

data_out2:

data_out3:

data_out4:

data_io1:

inoutSTD_LOGIC_VECTOR（3downto0）;

data_io2:

we3:

we4:

we_io1:

we_io2:

inSTD_LOGIC）;

enddata_bus;

architectureBehavioralofdata_busis

signalbus_data_reg:

STD_LOGIC_VECTOR（3downto0）;

signalout_en:

STD_LOGIC;

out_en<

='

0'

when（we1='

1'

orwe2='

orwe3='

orwe4='

orwe_io1='

orwe_io2='

）else'

data_io1<

=bus_data_regwhenout_en='

else"

ZZZZ"

data_io2<

data_out1<

=bus_data_reg;

data_out2<

data_out3<

data_out4<

process（clk）

ifclk'

eventandclk='

then

ifwe1='

bus_data_reg<

=data_in1;

elsifwe2='

=data_in2;

elsifwe3='

=data_in3;

elsifwe4='

=data_in4;

elsifwe_io1='

=data_io1;

elsifwe_io2='

=data_io2;

endif;

endif;