硬件结构设计Word文档下载推荐.docx

1、 LOC = M13; #Atlys LD4atlys_led5 LOC = D4; #Atlys LD5atlys_led6 LOC = P16; #Atlys LD6atlys_led7 LOC = N12; #Atlys LD7#-Atlys Switch input-atlys_sw0 LOC = A10; # Atlys sw0atlys_sw1 LOC = D14; # Atlys sw1atlys_sw2 LOC = C14; # Atlys sw2atlys_sw3 LOC = P15; # Atlys sw3atlys_sw4 LOC = P12; # Atlys sw4at

2、lys_sw5 LOC = R5; # Atlys sw5atlys_sw6 LOC = T5; # Atlys sw6atlys_sw7 LOC = E4; # Atlys sw7#-EES261 switch input-din0U11 #SW20din1R10 #SW19din2U10 #SW18din3R8 #SW17S0M8 #SW16S1U8 #SW15S2U7 #SW14S3N7 #SW13C_nT6 #SW12C_n_PlusR7 #SW11XLXN_9N6 #SW10swt8U5 #SW9swt7V5 #SW8swt6P7 #SW7swt5T7 #SW6swt4V6 #SW5

3、s0P8 #SW4s1V7 #SW3s2V8 #SW2s3N8 #SW1#-EES261 leds output-XLXN_21U16 #LED11U15 #LED22U13 #LED33M11 #LED4R11 #LED5ledT12 #LED66N10 #LED77M10 #LED8#-hex7seg-# NET anV16V15V13N11a_to_gN9 #e P11 #fV12 #gdpT11 #dp#-END-微程序控制操作方法：s0 s1 s2 s3 oen we1 we2 gwe1 oen_n1 gwe2 oen_n2 gwe3 oen_n3 0 0 0 0 1 0 0 0 1

4、 0 1 0 1 0 0 0 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 0 1 1 0 0 1 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 0 1 1 0微程序：Romc改编代码library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.std_logic_unsigned.a

5、ll; entity romc is Port （ s0 : in STD_LOGIC; s1 : s2 : s3 : oen : out STD_LOGIC; we1 : we2 : gwe1 : oen_n1 : gwe2 : oen_n2: gwe3 : oen_n3 : out STD_LOGIC ）;end romc;architecture Behavioral of romc is signal addr : std_logic_vector（1 downto 0）; -input signal rdata : std_logic_vector（3 downto 0）; -out

6、putbegin addr rdata 000000000 end case; end process; oen = rdata（0）; we1 = rdata（1）; we2 = rdata（2）; gwe1 = rdata（3）; oen_n1 = rdata（4）; gwe2 = rdata（5）; oen_n2 = rdata（6）; gwe3 = rdata（7）; oen_n3 = rdata（8）;end Behavioral;data_bus改编代码- Company: - Engineer:- - Create Date: 16:56:32 03/08/2013 - Desi

7、gn Name:- Module Name: data_bus - Behavioral - Project Name:- Target Devices:- Tool versions:- Description:- Dependencies:- Revision:- Revision 0.01 - File Created- Additional Comments:use IEEE.STD_LOGIC_1164.ALL;- Uncomment the following library declaration if using- arithmetic functions with Signe

8、d or Unsigned values-use IEEE.NUMERIC_STD.ALL;- Uncomment the following library declaration if instantiating- any Xilinx primitives in this code.-library UNISIM;-use UNISIM.VComponents.all;entity data_bus is Port （ clk : data_in1 : in STD_LOGIC_VECTOR （3 downto 0）; data_in2 : data_in3 : data_in4 : d

9、ata_out1 : out STD_LOGIC_VECTOR （3 downto 0）; data_out2 : data_out3 : data_out4 : data_io1 : inout STD_LOGIC_VECTOR （3 downto 0）; data_io2 : we3 : we4 : we_io1: we_io2: in STD_LOGIC）;end data_bus;architecture Behavioral of data_bus issignal bus_data_reg : STD_LOGIC_VECTOR （3downto 0）;signal out_en :

10、 STD_LOGIC; out_en = 0 when （we1=1 or we2= or we3= or we4= or we_io1 = or we_io2 = ） else data_io1 = bus_data_reg when out_en = else ZZZZ data_io2 data_out1 = bus_data_reg; data_out2 data_out3 data_out4 process（clk） if clkevent and clk = then if we1 = bus_data_reg = data_in1; elsif we2 = = data_in2; elsif we3 = = data_in3; elsif we4 = = data_in4; elsif we_io1 = = data_io1; elsif we_io2 = = data_io2; end if; end if;