16位模型机的设计说明Word格式.docx
《16位模型机的设计说明Word格式.docx》由会员分享,可在线阅读,更多相关《16位模型机的设计说明Word格式.docx(17页珍藏版)》请在冰豆网上搜索。
BRANCHINEXT;
转向NEXT
1.16位CPU的组成结构
2.指令系统的设计
一、指令格式
1)单字指令格式
2)双字指令格式
二、指令操作码
操作码
指令
功能
00001
LOAD
装载数据到寄存器
00010
STORE
将寄存器的数据存入到存储器
00100
LOADI
将立即数装入到寄存器
00101
BRANCHI
无条件转移到由立即数指定的地址
00110
BRANCHGTI
如果源寄存器容大于目的寄存器的容,则转移到由立即数指定的地址
00111
INC
寄存器容加1指令
依据以上设计的指令系统,则完成数据块复制的程序如下:
地址
机器码
功能说明
0000H
0001H
2001H
0010H
LOADIR1,0010H
0002H
0003H
2002H
0030H
LOADIR2,0030H
0004H
0005H
2006H
002FH
LOADIR6,002FH
0006H
080BH
LOADR3,[R1]
0007H
101AH
STORE[R2],R3
0008H
0009H
300EH
BRANCHGTI0000
如果R1大于R6,则转向地址0000
000AH
3801H
INCR1
000BH
3802H
INCR2
000CH
000DH
2800H
BRANCHI0006H
转向00006H,实现循环
3.VHDL设计
一、程序包:
说明运算器的功能、移动寄存器的操作、比较器的比较类型和用于CPU控制的状态类型。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
packagecpu_libis
subtypet_shiftisunsigned(3downto0);
constantshftpass:
unsigned(3downto0):
="
0000"
;
constantsftl:
0001"
constantsftr:
0010"
constantrotl:
0011"
constantrotr:
0100"
subtypet_aluisunsigned(3downto0);
constantalupass:
constantandOp:
constantorOp:
constantnotOp:
constantxorOp:
constantplus:
0101"
constantalusub:
0110"
constantinc:
0111"
constantdec:
1000"
constantzero:
1001"
subtypet_compisunsigned2downto0);
constanteq:
unsigned(2downto0):
000"
constantneq:
001"
constantgt:
010"
constantgte:
011"
constantlt:
100"
constantlte:
101"
subtypet_regisstd_logic_vector(2downto0);
typestateis(reset1,reset2,reset3,reset4,reset5,reset6,execute,nop,load,store,move,
load2,load3,load4,store2,store3,store4,move2,move3,move4,
incPc,incPc2,incPc3,incPc4,incPc5,incPc6,loadPc,loadPc2,loadPc3,loadPc4,
bgtI2,bgtI3,bgtI4,bgtI5,bgtI6,bgtI7,bgtI8,bgtI9,bgtI10,braI2,braI3,braI4,braI5,braI6,
loadI2,loadI3,loadI4,loadI5,loadI6,inc2,inc3,inc4);
subtypebit16isstd_logic_vector(15downto0);
endcpu_lib;
二、基本部件的设计
1)运算器的设计
功能
useieee.std_logic_unsigned.all;
usework.cpu_lib.all;
entityaluis
port(a,b:
inbit16;
sel:
int_alu;
c:
outbit16);
endalu;
architecturert1ofaluis
begin
process(a,b,sel)
caseselis
whenalupass=>
c<
=aafter1ns;
whenandop=>
=aandbafter1ns;
whenorop=>
=aorbafter1ns;
whenxorop=>
=axorbafter1ns;
whennotop=>
=notaafter1ns;
whenplus=>
=a+bafter1ns;
whenalusub=>
=a-bafter1ns;
wheninc=>
=a+"
00001"
after1ns;
whendec=>
=a-"
whenzero=>
00000"
whenothers=>
endcase;
endprocess;
endrt1;
2)比较器
entitycompis
port(a,b:
int_comp;
compout:
outbit);
endcomp;
architecturert1ofcompis
process(a,b,sel)
caseselis
wheneq=>
ifa=bthencompout<
='
1'
elsecompout<
0'
endif;
whenneq=>
ifa/=bthencompout<
whengt=>
ifa>
bthencompout<
whengte=>
=bthencompout<
whenlt=>
ifa<
whenlte=>
whenothers=>
compout<
3)移位寄存器
entityshiftis
port(a:
int_shift;
y:
endshift;
architecturert1ofshiftis
process(a,sel)
whenshftpass=>
y<
=aafter1ns;
whensftl=>
=a(14downto0)&
'
after1ns;
whensftr=>
&
a(15downto1)after1ns;
whenrotl=>
a(15)after1ns;
whenrotr=>
=a(0)&
whenothers=>
4)寄存器
useieee.std_