东南大学CPU报告Word格式文档下载.doc

东南大学CPU报告Word格式文档下载.doc

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MAR（MemoryAddressRegister） 3

MBR（MemoryBufferRegister） 4

PC（ProgramCounter） 4

IR（InstructionRegister） 4

ACC（Accumulator） 5

MR（MultiplierRegister） 5

DR（DivisionRegister） 5

LPM_RAM_DQ 5

ALU（ArithmeticLogicUnit） 6

Micro-programmedControlUnit 6

CPUArchitecture 8

ControlsignalsinControlMemory 8

ContentsofControlMemory 9

Toplevelcircuitdiagram 11

Simulationresults:

12

Problem1:

Calculatethesumofallintegersfrom1to100 12

Problem2:

Calculate300and275 14

ResultsAnalysis 14

FurtherImprovement 15

Reference 15

Appendix 15

1．MBRmodule 15

2．BRmodule 16

3．ALUmodule 17

4．IRmodule 18

5．PCmodule 19

6．MARmodule 20

7．control_unitmodule 21

8．MRmodule 22

Purpose

ThepurposeofthisprojectistodesignasimpleCPU（CentralProcessingUnit）.ThisCPUhasbasicinstructionset,andwewillutilizeitsinstructionsettogenerateaverysimpleprogramtoverifyitsperformance.Forsimplicity,wewillonlyconsidertherelationshipamongtheCPU,registers,memoryandinstructionset.Thatistosayweonlyneedtoconsiderthefollowingitems:

Read/WriteRegisters,Read/WriteMemoryandexecutetheinstructions.

AtleastfourpartsconstituteasimpleCPU:

thecontrolunit,theinternalregisters,theALUandinstructionset,whicharethemainaspectsofourprojectdesignandwillbestudied.

ExperimentPrinciple

InstructionSet

Single-addressinstructionformatisusedinoursimpleCPUdesign.Theinstructionwordcontainstwosections:

theoperationcode（opcode）,whichdefinesthefunctionofinstructions（addition,subtraction,logicoperations,etc.）;

theaddresspart,inmostinstructions,theaddresspartcontainsthememorylocationofthedatumtobeoperated,wecalleditdirectaddressing.Insomeinstructions,theaddresspartistheoperand,whichiscalledimmediateaddressing.

Forsimplicity,thesizeofmemoryis256×

16inthecomputer.Theinstructionwordhas16bits.Theopcodeparthas8bitsandaddressparthas8bits.TheinstructionwordformatcanbeexpressedinFigure1

OPCODE[15:

8]

ADDRESS[7:

0]

Figure1theinstructionformat

TheopcodeoftherelevantinstructionsarelistedinTable1.InTable1,thenotation[x]representsthecontentsofthelocationxinthememory.Forexample,theinstructionword00000011101110012（03B916）meansthattheCPUaddswordatlocationB916inmemoryintotheaccumulator（ACC）;

theinstructionword00000101000001112（050716）meansifthesignbitoftheACC（ACC[15]）is0,theCPUwillusetheaddresspartoftheinstructionastheaddressofnextinstruction,ifthesignbitis1,theCPUwillincreasetheprogramcounter（PC）anduseitscontent

InternalRegistersandMemory

MAR（MemoryAddressRegister）

MARcontainsthememorylocationofthewordtobereadfromthememoryorwrittenintothememory.Here,READoperationisdenotedastheCPUreadsfrommemory,andWRITEoperationisdenotedastheCPUwritestomemory.Inourdesign,MARhas8bitstoaccessoneof256addressesofthememory.

Inmyexperiment,theMARblockisasfigure2

Figure2

MBR（MemoryBufferRegister）

MBRcontainsthevaluetobestoredinmemoryorthelastvaluereadfrommemory.MBRisconnectedtotheaddresslinesofthesystembus.Inourdesign,MBRhas16bits.

Inmyexperiment,theMBRblockisasfigure3

Figure3

PC（ProgramCounter）

PCkeepstrackoftheinstructionstobeusedintheprogram.Inourdesign,PChas8bits.

Inmyexperiment,thePCblockisasfigure4

Figure4

IR（InstructionRegister）

IRcontainstheopcodepartofaninstruction.Inourdesign,IRhas8bits.BR（BufferRegister）BRisusedasaninputofALU,itholdsotheroperandforALU.Inourdesign,BRhas16bits.

Inmyexperiment,theInstructionregisterisasfigure5

Figure5

ACC（Accumulator）

ACCholdsoneoperandforALU,andgenerallyACCholdsthecalculationresultofALU.Inourdesign,ACChas16bits.

MR（MultiplierRegister）

MRisusedforimplementingtheMPYinstruction,holdingthemultiplieratthebeginningoftheinstruction.Whentheinstructionisexecuted,itholdspartoftheproduct.

Inmyexperiment,theMRisasfigure6

Figure6

DR（DivisionRegister）

DRisusedforimplementingtheDIVinstruction,youcandefineitaccordingtoyourdivisionalgorithm.It’soptional.Here,weignoreit.

LPM_RAM_DQ

LPM_RAM_DQisaRAMwithseparateinputandoutputports,itworksasmemory,anditssizeis256×

16.Althoughit’snotaninternalregisterofCPU,weneedittosimulateandtesttheperformanceofCPU.Alltheregistersarepositive-edge-triggered.AlltheresetsignalsfortheregistersareALU.

Figure7

ALU（ArithmeticLogicUnit）

ALU