东南大学CPU报告Word格式文档下载.doc

1、MAR （Memory Address Register）3MBR （Memory Buffer Register）4PC （Program Counter）4IR （Instruction Register）4ACC （Accumulator）5MR （Multiplier Register）5DR （Division Register）5LPM_RAM_DQ5ALU （Arithmetic Logic Unit）6Micro-programmed Control Unit6CPU Architecture8Control signals in Control Memory8Contents

2、 of Control Memory9Top level circuit diagram11Simulation results:12Problem 1: Calculate the sum of all integers from 1 to 10012Problem 2: Calculate 300 and 27514Results Analysis14Further Improvement15Reference15Appendix151MBR module152BR module163ALU module174IR module185PC module196MAR module207con

3、trol_unit module218MR module22PurposeThe purpose of this project is to design a simple CPU （Central Processing Unit）. This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to verify its performance. For simplicity, we will only consider the rel

4、ationship among the CPU, registers, memory and instruction set. That is to say we only need to consider the following items: Read/Write Registers, Read/Write Memory and execute the instructions. At least four parts constitute a simple CPU: the control unit, the internal registers, the ALU and instru

5、ction set, which are the main aspects of our project design and will be studied.Experiment PrincipleInstruction SetSingle-address instruction format is used in our simple CPU design. The instruction word contains two sections: the operation code （opcode）, which defines the function of instructions （

6、addition, subtraction, logic operations, etc.）; the address part, in most instructions, the address part contains the memory location of the datum to be operated, we called it direct addressing. In some instructions, the address part is the operand, which is called immediate addressing. For simplici

7、ty, the size of memory is 25616 in the computer. The instruction word has 16 bits. The opcode part has 8 bits and address part has 8 bits. The instruction word format can be expressed in Figure 1OPCODE15:8ADDRESS7:0Figure 1 the instruction formatThe opcode of the relevant instructions are listed in

8、Table 1. In Table 1, the notation x represents the contents of the location x in the memory. For example, the instruction word 00000011101110012 （03B916） means that the CPU adds word at location B916 in memory into the accumulator （ACC）; the instruction word 00000101000001112 （050716） means if the s

9、ign bit of the ACC （ACC 15） is 0, the CPU will use the address part of the instruction as the address of next instruction, if the sign bit is 1, the CPU will increase the program counter （PC） and use its contentInternal Registers and Memory MAR （Memory Address Register） MAR contains the memory locat

10、ion of the word to be read from the memory or written into the memory. Here, READ operation is denoted as the CPU reads from memory, and WRITE operation is denoted as the CPU writes to memory. In our design, MAR has 8 bits to access one of 256 addresses of the memory. In my experiment, the MAR block

11、 is as figure 2Figure 2MBR （Memory Buffer Register） MBR contains the value to be stored in memory or the last value read from memory. MBR is connected to the address lines of the system bus. In our design, MBR has 16 bits. In my experiment, the MBR block is as figure 3Figure 3PC （Program Counter） PC

12、 keeps track of the instructions to be used in the program. In our design, PC has 8 bits. In my experiment, the PC block is as figure 4Figure 4IR （Instruction Register） IR contains the opcode part of an instruction. In our design, IR has 8 bits. BR （Buffer Register） BR is used as an input of ALU, it

13、 holds other operand for ALU. In our design, BR has 16 bits. In my experiment, the Instruction register is as figure 5Figure 5ACC （Accumulator） ACC holds one operand for ALU, and generally ACC holds the calculation result of ALU. In our design, ACC has 16 bits. MR （Multiplier Register） MR is used fo

14、r implementing the MPY instruction, holding the multiplier at the beginning of the instruction. When the instruction is executed, it holds part of the product. In my experiment, the MR is as figure 6Figure 6DR （Division Register） DR is used for implementing the DIV instruction, you can define it acc

15、ording to your division algorithm. Its optional. Here, we ignore it.LPM_RAM_DQ LPM_RAM_DQ is a RAM with separate input and output ports, it works as memory, and its size is 25616. Although its not an internal register of CPU, we need it to simulate and test the performance of CPU. All the registers are positive-edge-triggered. All the reset signals for the registers are ALU .Figure 7ALU （Arithmetic Logic Unit） ALU