大连交通大学coa考试题2.docx
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大连交通大学coa考试题2
I.Supposebothinstructionsanddataare16bitslong,theopcodefieldin4bitslong,thereisaprogramfragment(程序段)withthreeinstructionsstoredfrommemorylocation300to302andtwodataitemsstoredinmemorylocation941and942,allthenumberarehexadecimal(十六进制数)inthefigure.(16points)
(Notes:
LoadxmeansLoadACfrommemorylocationx;
StorexmeansStoreACtomemorylocationx;
Add(x)meansOperandpointedbythecontentoflocationXisaddedtoAC)
Answerthefollowingquestions:
(Puttheansweronthenextpage)
(1)GivethePCvaluebeforeandaftertheprogramfragmentexecution.(2points)
(2)Tellthefinalresultofmemorylocation941.(2points)
(3)Telltheaddressingmodeandaddressingrangeoftheinstructionstoredinmemorylocation300and301.(6points)
(4)Writeouttheallthemicro-operationoftheinstructionsstoredinmemorylocation301.(6points)
。
。
300
Load941
301
Add(500)
302
Store941
。
。
500
942
。
。
941
0941
942
0942
Answer:
1.before:
(PC)=___300_____(1points)
After:
(PC)=___303_____(1points)
2.Finalresultofmemorylocation941:
(941)=___1283_____(2points)
3.instructionstoredinmemorylocation300:
Addressingmode:
__direct____(1points)
Addressingrange:
__212=4K__(2points)
instructionstoredinmemorylocation301:
Addressingmode:
__indirect__(1points)
Addressingrange:
__216=64K_(2points)
4.Writeoutthemicro-operationoftheinstructionsstoredinmemorylocation301.Add(500);
FetchcycleIndirectcycleExecutecycle
t1:
(PC)->MARt1:
Ad(MBR)->MARt1:
(MBR)->MAR
t2:
(MAR)--->Memoryt2:
(MAR)->Memoryt2:
(MAR)->Memory
read--->Memoryread->Memoryread->Memory
t3:
Memory--->MBRt3:
Memory->MBRt3:
Memory->MBR
t4:
(MBR)->IRt4:
(MBR)+(AC)->AC
(PC)+1->PC
(2points)(2points)(2points)
II.Asetassociativecacheconsistsof32klines,dividedinto8-linesets.Mainmemorycontains16Mblocksof256wordseach.Answerthefollowingquestions:
(16points)
(1)Showtheformatofthemainmemoryaddress.(7points)
(2)Foracertainblockofmainmemory,howmanycachelinescanitmapto?
(2points)
(3)Foracertainlineofcachememory,howmanyblocksofmainmemorymaybemappedto?
(2points)
(4)WhereinthecacheisthewordfrommemorylocationABCDE8F8mapped?
(5points)
Answer:
(1)1)Linesize=Blocksize=256words=28words=>Word#=8bits(1points)
2)Numberofsets=32klines/8lines/set=212sets=>Set#=12bits(2points)
3)Memorysize=16Mx256words=232words=>LengthofRA=32bits=>Tag=32-12-8=12bits(2points)
so,addressformatis:
(2points)
tagset#word#
12-bit
12-bit
8-bit
(2)8lines(2points)
(3)2Tag=212=4Kblocks(2points)
(4)ABCDE8F8H=1010,1011,1100,1101,1110,1000,1111,1000(2points)
Tag=ABCHSET#=DE8H(2points)
memorylocationABCDE8F8canbemappedtoanylineofsetDE8H,tag=ABCH(1points)
III.SupposetheHammingcode010111010101isjustreadfrommemory,pleaseusetheHammingalgorithmtodeterminewhatisthe
valid8-bitdata?
(14points)
(1)2k-1≥m+km=8=>k=4-bit(1points)
(2)Setupatable(3points)
BitPosition
Positionnumber
Checkbit
Databit
12
1100
D8
0
11
1011
D7
1
10
1010
D6
0
9
1001
D5
1
8
1000
C8
1
7
0111
D4
1
6
0110
D3
0
5
0101
D2
1
4
0100
C4
0
3
0011
D1
1
2
0010
C2
0
1
0001
C1
1
C8C4C2C1=1001(1points)
D8D7D6D5D4D3D2D1=01011011(1points)
(3)Calculatesnewcheckbits:
C1’(1,2,4,5,7)=1⊕1⊕1⊕1⊕1=1(1points)
C2’(1,3,4,6,7)=1⊕0⊕1⊕0⊕1=1(1points)
C4’(2,3,4,8)=1⊕0⊕1⊕0=0(1points)
C8’(5,6,7,8)=1⊕0⊕1⊕0=0(1points)
=>newcheckbits:
C8’C4’C2’C1’=0011
(4)syndromewords=C8C4C2C1⊕C8’C4’C2’C1’=1001⊕0011=1010(2points)
D6hasanerror,socorrectD6=1(1points)
Socorrectdatabit:
01111011(1points)
IV.Inmulti-processorsystems,MESIprotocolisusedtosolvetheproblemofcachecoherence.Accordingtothegivenfigure,answerthefollowingquestions:
InitialSnoopy
1)(14points)Thisisthecaseof_________.
2)Pleasecompletethisfigure.
3)Withthiscase,pleasefillbestanswersintothefollowingtable.
Thestatesinbegin
WhereistheValiddata?
Actions
Thestatesinend
Initial
snoopy
Initial
snoopy
1)Thisisthecaseof___writehit______.
2)Pleasecompletethisfigure.
3)Withthiscase,pleasefillbestanswersintothefollowingtable.
Thestatesinbegin
WhereistheValiddata?
Actions
Thestatesinend
Initial
snoopy
Initial
snoopy
E
I
ThecacheinExclusivestateandMM.
Theinitialjustupdatestheword,andtransitionstomodifiedstate.
M
I
S
S
ThecacheinsharedstateandMM
Theinitialsignalsitsexclusiveownershipofthecachelineonthebus,thesnoopyinsharedstatetransitionstoinvalidstate.Theinitialupdatesthewordandtransitionstomodifiedstate,
M
I
M
I
Onlythecacheinmodifiedstate
Theinitialupdatesthewordandstillinmodifiedstate.
M
I
V.Trueorfalse(true:
√,false:
×)
()1.TheFIFOcharacteristicsofstackmakesitcapableofhelpingimplementingnestedprocedurecallandnestedinterrupthandling.
()2.Morethanonemodulemaycontrolbusatonetime.
()3.Theoperationcodemustnotbeincludedinaninstruction.
()4.Addressbuswidthis32bits,soaddressingrangeis4M.
()5.ForRAID5,paritystripesacrossalldisks,roundrobinallocationforparitystripe,avoidsRAID4bottleneckatparitydisk.
()6.Indexaddressingmodeisgoodforaccessingarrays.
()7.Inamultipleplattersharddisksystem,alignedtracksoneachplatterformcylinder.
()8.Incomputer,addressinformationcanbeviewedasunsignedinteger.
()9.Theworstfactortoaffectinstructionpipelineeffectivenessisbranchinstruction.
()10.Cachemechanismbasesonthefactthatduringthecourseoftheexecutionofaprogram,memoryreferencestendtocluster,thisreferstoaslocalityofreference.
II.Trueorfalse(true:
√,false:
×)
(×)1.TheFIFOcharacteristicsofstackmakesitcapableofhelpingimplementingnestedprocedurecallandnestedinterrupthandling.
(×)2.Morethanonemodulemaycontrolbusatonetime.
(×)3.Theoperationcodemustnotbeincludedinaninstruction.
(×)4.Addressbuswidthis32bits,soaddressingrangeis4M.
(√)5.ForRAID5,paritystripesacrossalldisks,roundrobinallocationforparitystripe,avoidsRAID4bottleneckatparitydisk.
(√)6.Indexaddressingmodeisgoodforaccessingarrays.
(√)7.Inamultipleplattersharddisksystem,alignedtracksoneachplatterformcylinder.
(√)8.Incomputer,addressinformationcanbeviewedasunsignedinteger.
(×)9.Theworstfactortoaffectinstructionpipelineeffectivenessisbranchinstruction.
(√)10.Cachemechanismbasesonthefactthatduringthecourseoftheexecutionofaprogram,memoryreferencestendtocluster,thisreferstoaslocalityofreference.
1.Controlunitusessomeinputsignalstoproducecontrolsignalsthatopenthegatesofinformationpathsandletthemicro-operationsimplement.WhichisNOTtheoutputsignalsofcontrolunit?
_______
A.subtractioncontrolsignaltoALUB.clockandflags
C.controlsignalstotheI/OmodulesD.memoryreadandwrite
2.An8-bittwoscomplementdata10011001isextendedtoa16-bitdatathatequalsto_____
A.1000000000011001B.0000000010011001
C.1111111110011001D.1111111101100111
3.The_____registerisuseedtopointtothetopofstack
A.PCB.SPC.MARD.MBR
4.Therangeofan8-bittwo’scomplementrepresentationisbetween_________.
A.-127to+127B.-128to127
C.0to255D.-128to128
5.Whichofthefollowingtypesfomemorysierasablesemiconductormemory?
_____
A.DVD-RWB.HarddiskC.cacheD.maskROM
6.Thecorrectsequencesofinterruptprecessstemsare__________
A.suspending,branching,processing&resuming
B.branching,suspending,processing&resuming
C.suspending,resuming,branching&processing
D.processing,branching,resuming&suspending
7.Withmappingfunctionofcache,anyblockofmainmemorycanbemappedtoanylineofcache,itis________.
A.AssociativeMappingB.directMapping
C.SetAssociativeMappingD.RandomMapping
8.Whichofthefollowinginteger(n=8,representedintwo’scomplement)willnotcauseoverflowafterarithmeticshiftleftonebitoperation?
_____
A.00110111B.01000000C.10110111D.01111011
9.Thedifferencebetweentightlycoupledsystemandlooselycoupledsystemis____?
A.tightlycoupledexecuteasingleinstruction,looselycoupledexecutesdifferentinstruction
B.tightlycoupledhassharedmemory,looselycoupledhasdistributedmemory
C.tightlycoupledoperatesonasingledataset,looselycoupledoperatesondifferentdataset
D.tightlycoupledhassingleCPU,looselycoupledhasasetofCPU
10.ComparingwithprogrammedI/O,interrupt-driverI/OfurtherraisestheusagerateofCPUoperations,because__________.
A.itisn’tnecessaryforCPUtosave&restorescene
B.itisn’tnecessaryforCPUtointervensthedatatransfer
C.bothAandB
D.itisn’tnecessaryforCPUtoread&checkstatusrepeatedly
11.InDMA,theDMAmoduletakesovertheoperationsofdatatransferringfromCPU,itmeans_______________.
A.theDMAmodulecanfetchandexecuteinstructionslikeCPUdoes
B.theDMAmodulecanholdthebustotransferdatatoorfrommemoryusingstealingcycletechnique
C.theDMAmoduleandCPUworktogether(co-operate)totransferdataintoorfrommemory
D.whenDMAmodulegetsready,itissueinterruptrequestsignaltoCPUforgettingi