东南大学信息学院 poc实验报告.docx
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东南大学信息学院poc实验报告
ComputerOrganizationandArchitectureCOURSEDESIGN
AParallelOutputController
------(POC)
Southeastuniversity
SchoolofInformationScienceandEngineering
1.Designpurpose
a.Thepurposeofthisprojectistodesignandsimulateaparalleloutputcontroller(POC)whichactsaninterfacebetweensystembusandprinter.TheISE14.7EDAtoolisrecommendedandprovidedforsimulation.
b.LearnabouttheusingofBi-directionalDataBus(BDB),anduseaparallelBi-directionalDataBustofinishthedatatransmissionbetweenCPUandPOC.
2.IntroductionandTasks
POCisoneofthemostcommonI/Omodules,namelytheparalleloutputcontroller.Itplaystheroleofaninterfacebetweenthecomputersystembusandtheperipheral
Figure1.Systemstructurediagram
AsFig.1showstheinnerconnectingofaprintertothesystembusthroughthePOC.The-municationbetweenPOCandtheprinteriscontrolledbya“handshake”protocolgiveninFig.2.
Figure2.Thehandshake-timingdiagrambetweenPOCandtheprinter
Thehandshakingprocessisdescribedasfollows:
Whentheprinterisreadytoreceiveachar-acter,itholdsRDY=1.ThePOCmustthenholdacharacteratPD(paralleldata)portandproduceapulseattheterminalTR(transferrequest).TheprinterwillchangeRDYto0,takethecharacter
atPDandholdRDYat0untilthecharacterhasbeenprinted(e.g.delay5or10ms),thensetRDYto1againwhenitisreadytoreceivethenextcharacter.
ThebufferregisterBRisusedtotemporarilyholdacharactersentfromtheprocessor,whichchar-acterwillbetransferredtotheprinterlater.
ThestatusregisterSRisusedfortwocontrolfunctions:
①SR7servesasareadyflagtoindicatePOCisreadyornottoreceiveanewcharacterfromtheprocessor.
②SR0isusedtoenabletheinterruptrequestssentbyPOC.
Ininterruptmode,IfSR0=1,thenPOCwillsendaninterruptrequestsignaltoprocessorwhenitisreadytoreceiveacharacter(i.e.,whenSR7=1).
IfSR0=0,thenPOCwillnotinterrupt.
ThetransferofacharactertoPOCviathesystembusproceedsasfollows:
Ininterruptmode,SR0isalways1.
Aftersendingcharactertoprinter,POCsetstheSR7to1,sinceSR0=1,theinterruptrequestsignal(IRQ)issetto0,whichindicateaneffectiveinterruptsignaltotheprocessor.
1、processorsetsthevalueofSR7&setsthevalueofBR
①WhentheprocessordetectstheeffectiveIRQsignal,theprocessordirectlyselectsBRandwritesacharacterintoBR,(processorwillneverreadthestateofSR7,whichisdifferentwithpollingmode.)
②ThentheprocessorsetstheSR7to0,whichindicatesthatthenewcharacterhasbeenwritteninto
BRandnotprintedyet.
2、POCreadsandsetsthevalueofSR7&handshakesoperationswiththeprinter
①WhenPOCdetectsthatSR7issetto0,POCthenproceedstostartthehandshakingoperationswiththeprinter.
②Aftersendingcharactertoprinter,POCsetstheSR7to1,whichindicatesPOCisreadytoreceiveanothercharacterfromtheprocessor.Thetransfercyclecannowrepeat.(①and②aresamewiththepollingstate)
PS:
DuringthehandshakingoperationsbetweenPOCandprinter,theprocessordoesnottrytoaccessPOCuntilitreceivestheinterruptrequestsignal
3.TheoverallconnectionofthesimulatedprinterandPOCexpressedinthetopmoduleform
Figure3.Thetopmoduleformoftheproject
4.Designdescriptionofthesimulationinputwaveforms
TheinputandoutputofCPU,POCandprinterareshownbelow:
Processorj
Pins
Description
Input
clk
InputtheclockfortheCPUrunning.
mode
Choosethemodeforprinting.
Whenmode=’1’,selectainterruptmode.
IRQ
ReceivetheinterruptsignalIRQ.
WhenIRQ='1',newdatacanbesent.
DIN[7..0]
Readdatafrompoc.
DOUT[7..0]
Writedataintopoc.
Output
rw
ShowthedirectionoftheDOUT[7..0]andDIN[7..0]Whenrw='0',readdatafromPOC.
When'rw'='1',writedatatoPOC.
A0
ControltheaddressreadandwriteonPOC.
WhenA0='0',chooseSR.
WhenA0='1',chooseBR.
CS
CS=‘1’,pocwork.
data[7..0]
ThedatasendtoPOCtobeprinted
POC
Pins
Description
Input
clk
InputtheclockforthePOCrunning.
RW
ShowthedirectionoftheDOUT[7..0]andDIN[7..0]Whenrw='0',senddatatoCPU.
When'rw'='1',readdatafromCPU.
A0
Inputaddress,
WhenA0='0',chooseBR.WhenA0='1',chooseSR.
RDY
Inputthereadysignalfromprinter.WhenRDY='1',theprinterisidle.
WhenRDY='0',theprinterisbusy.
CS
InputthemodeofthePOC.
WhenCS=’0’,selectapollingmode.WhenCS=’1’,selectainterruptmode.
data[7..0]
ThedatareceivefromCPUtobeprinted.
Output
PD[7..0]
Outputthedatatoprinter.
IRQ
OutputtheinterruptsignalIRQtoCPU,
showingthePOCandprinterisready.
TR
Theresponsetoprint'RDYsignal,aone-cyclepulseattheportTR
(transferrequest)showsthatnewdataissenttoprinter.
DOUT[7..0]
CS=0POCsendthestateofSRtoCPU;
CS=1CPUreadthedatawriteinBR
Signal
SR[7..0]
TheregistercontainstheflagsforthePOC.WhenSR(7)='1',it'sidle.
WhenSR(7)='0',it'sbusy.
BR[7..0]
Theregisterholdsthevalueofdatatoprint.
printer
Pins
Description
Input
clk
Inputtheclockfortheprinterrunning.
TR
InputthepulsesignalfromPOC,toshownewdataiscoming.
PD[7..0]
InputthedatafromPOC.
Output
RDY
OutputRDYsignal,
whenRDY='1',itshowsprinteriswaitingfornewdata.
5.Simulationresults
Connectionbetweencpuandpoc
Connectionbetweenpocandprinter
Herearetheexplanationsofthesimulationwave:
interruptmode:
1、Intheinterruptmode,modeisalwaysset1,theprintprocessoccuresbytheIRQsignalfrompoc.
2、WhenS(7)=0,IRAsend‘0’tocpu,itmeansthereisaprintrequirementandcpubegintohandleit.
3、IntheinterruptprocessRWandA0aresingalsfromcputopoctocontroltheactionofpoc.
RW=’1’andA0=’1’writedatafromcpu(D)topoc(BR),meansthebeginoftheinterruptprocess.
RW=’x’andA0=’x’meansthereisnointerruptrequirement.
4、AftersendingdatastoBRandsetsrto“00000000”,ifRDY=’1’,pocgiveaimpulseinTRtomaketheprinterbegintowork.AftertheTRsignalwecanseethattheinputRDYsignalfromtheprinterchangefrom1to0,whichshowsthattheTRsignalreallymaketheprinterwork.
5、AfterdataofBRhasbeentransmittedintoprinter,pocsetSRto“10000001”itselftoindicatethatitcomestoreadyandcangetthenextprinttask.
6、Letdataplus1toindicatethenextnewprintcycle.
6.ConclusionandDiscussions
1、Asaparalleloutputcontroller,pocmoduletoactasaninterfacebetweencpuandprinter.Formthesimulationwave,wecanseethatmyprogrammeetsthedesignsrequirements.
2、Idividethesystemintothreeparts,andonetopentity.AndIusetwowaytofinish
thetopentity.Oneiswriteprogramwithvhdllanguageandanotheriscreatea
schematictypefileandconnectwire.
3、BydesigningthePOCmodule,IfindithelpstolearnhowtouseofquartusandVHDLfordesignandsimulation.Theprocessofdesigningalsoteachsmetheimportantceoffiguringoutthestruc-tureandtimingofthetaskbeforeprogramming.
Appendix:
Theprogramofprocessor:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entityprocessoris
port
(
clk:
instd_logic;
IRQ:
instd_logic;
DOUT:
outstd_logic_vector(7downto0):
="00000000";
RW:
outstd_logic:
='0';--0read,1write
A0:
outstd_logic:
='0';--0sr,1br
DIN:
instd_logic_vector(7downto0)
);
endprocessor;
architectureBehavioralofprocessoris
signaldata:
std_logic_vector(7downto0):
="00000000";
signalmode:
std_logic:
='1';--默认为中断模式
begin
process(clk)
begin
ifclk'eventandclk='1'then
ifmode='1'then
ifIRQ='0'then
A0<='1';
RW<='1';--写入数据到BR
data<=data+"00000001";--代表传输的字符
DOUT<=data;
else
A0<='X';
RW<='X';--读入SR的数据
endif;
endif;
endif;
endprocess;
endBehavioral;
theprogramofpoc:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useieee.std_logic_arith.ALL;
useieee.std_logic_unsigned.ALL;
--Uncommentthefollowinglibrarydeclarationifusing
--arithmeticfunctionswithSignedorUnsignedvalues
--useIEEE.NUMERIC_STD.ALL;
--Uncommentthefollowinglibrarydeclarationifinstantiating
--anyXilinxprimitivesinthiscode.
--libraryUNISIM;
--useUNISIM.VComponents.all;
entitypocis
port
(
A0:
instd_logic;
RW:
instd_logic;
clk:
instd_logic;
CS:
instd_logic:
='1';
RDY:
instd_logic;
IRQ:
outstd_logic:
='1';
DOUT:
outstd_logic_vector(7downto0);
PD:
outstd_logic_vector(7downto0);
TR:
outstd_logic:
='0';
DIN:
instd_logic_vector(7downto0)
);
endpoc;
architectureBehavioralofpocis
signalSR:
std_logic_vector(7downto0):
="10000001";
signalBR:
std_logic_vector(7downto0):
="00000000";
signalcount:
integerrange0to5:
=0;
typestate_typeis(s0,s1,s2);
signalstate:
state_type:
=s0;
begin
process(clk)
begin
ifclk'eventandclk='1'then
TR<='0';
IRQ<='1';
casestateis
whens0=>----中断请求信号
ifSR(7)='1'then
IRQ<='0';--中断请求
state<=s1;
else
IRQ<='1';
state<=s2;--无中断请求
endif;
whens1=>----读入读出选择
ifRW='1'andA0='1'then--cpu写入数据到BR
BR<=DIN;
SR(7)<='0';
state<=s2;
elsifRW='0'andA0='0'then--cpu读入SR的数据
DOUT<=SR;
elsifRW='1'andA0='0'then--cpu写入数据到SR
SR<=DIN;
elsifRW='0'andA0='1'then--cpu读入BR的数据
DOUT<=