交通灯控制电路设计及仿真.docx
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交通灯控制电路设计及仿真
交通灯控制电路设计与仿真
一、实验目的
1、了解交通灯的燃灭规律。
2、了解交通灯控制器的工作原理。
3、熟悉VHDL语言编程，了解实际设计中的优化方案。
二、实验原理
交通灯的显示有很多方式，如十字路口、丁字路口等，而对于同一个路口又有很多不同的显示要求，比如十字路口，车辆如果只要东西和南北方向通行就很简单，而如果车子可以左右转弯的通行就比较复杂，本实验仅针对最简单的南北和东西直行的情况。
要完成本实验，首先必须了解交通路灯的燃灭规律。
本实验需要用到实验箱上交通灯模块中的发光二极管，即红、黄、绿各三个。
依人们的交通常规，“红灯停，绿灯行，黄灯提醒”。
其交通的燃灭规律为：
初始态是两个路口的红灯全亮，之后，东西路口的绿灯亮，南北路口的红灯亮，东西方向通车，延时一段时间后，东西路口绿灯灭，黄灯开始闪烁。
闪烁若干次后，东西路口红灯亮，而同时南北路口的绿灯亮，南北方向开始通车，延时一段时间后，南北路口的绿灯灭，黄灯开始闪烁。
闪烁若干次后，再切换到东西路口方向，重复上述过程。
在实验中使用8个七段码管中的任意两个数码管显示时间。
东西路和南北路的通车时间均设定为20s。
数码管的时间总是显示为19、18、17……2、1、0、19、18……。
在显示时间小于3秒的时候，通车方向的黄灯闪烁。
三、实验内容
本实验要完成任务就是设计一个简单的交通灯控制器，交通灯显示用实验箱
的交通灯模块和七段码管中的任意两个来显示。
系统时钟选择时钟模块的1KHz
时钟，黄灯闪烁时钟要求为2Hz，七段码管的时间显示为1Hz脉冲，即每1s中递
减一次，在显示时间小于3秒的时候，通车方向的黄灯以2Hz的频率闪烁。
系统
中用S1按键进行复位。
实验箱中用到的数字时钟模块、按键开关、数码管与FPGA的接口电路，以及
数字时钟源、按键开关、数码管与FPGA的管脚连接在以前的实验中都做了详细说
明，这里不在赘述。
交通灯模块原理与LED灯模块的电路原理一致，当有高电平输
入时LED灯就会被点亮，反之不亮。
只是LED发出的光有颜色之分。
其与FPGA的
管脚连接如下表19-1所示：
四、实验步骤
1、打开QUARTUSII软件，新建一个工程。
2、建完工程之后，再新建一个VHDLFile，打开VHDL编辑器对话框。
3、按照实验原理和自己的想法，在VHDL编辑窗口编写VHDL程序，用户
可参照光盘中提供的示例程序。
4、编写完VHDL程序后，保存起来。
（1）-jtdkz.vhd
libraryieee;
useieee.std_logic_1164.all;
entityjtdkzis
port（clk,sm,sb:
instd_logic;
mr,my0,mg0,br,by0,bg0:
outstd_logic）;
endentityjtdkz;
architectureartofjtdkzis
typestate_typeis（A,B,C,D）;
signalstate:
state_type;
begin
t:
process（clk）is
variables:
integerrange0to45;
variableclr,en:
bit;
begin
if（clk'eventandclk='1'）then
ifclr='0'thens:
=0;
elsifen='0'thens:
=s;
elses:
=s+1;
endif;
casestateis
whenA=>mr<='0';my0<='0';mg0<='1';br<='1';by0<='0';bg0<='0';
if（sbandsm）='1'then
ifs=45thenstate<=B;clr:
='0';en:
='0';
elsestate<=A;clr:
='1';en:
='1';
endif;
elsif（sband（notsm））='1'thenstate<=B;clr:
='0';en:
='0';
elsestate<=A;clr:
='1';en:
='1';
endif;
whenB=>mr<='0';my0<='1';mg0<='0';br<='1';by0<='0';bg0<='0';
ifs=5thenstate<=C;clr:
='0';en:
='0';
elsestate<=B;clr:
='1';en:
='1';
endif;
whenC=>mr<='1';my0<='0';mg0<='0';br<='0';by0<='0';bg0<='1';
if（sbandsm）='1'then
ifs=25thenstate<=D;clr:
='0';en:
='0';
elsestate<=C;clr:
='1';en:
='1';
endif;
elsifsb='0'thenstate<=D;clr:
='0';en:
='0';
elsestate<=C;clr:
='1';en:
='1';
endif;
whenD=>mr<='1';my0<='0';mg0<='0';br<='0';by0<='1';bg0<='0';
ifs=5thenstate<=A;clr:
='0';en:
='0';
elsestate<=D;clr:
='1';en:
='1';
endif;
endcase;
endif;
endprocesst;
endarchitectureart;
（2）cskz.vhd
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitycskzis
port（ina:
instd_logic;
outa:
outstd_logic）;
endentitycskz;
architectureartofcskzis
begin
process（ina）is
begin
ifina='1'thenouta<='1';
elseouta<='0';
endif;
endprocess;
endarchitectureart;
（3）—t45s.vhd
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityt45sis
port（sb,clk,en45:
instd_logic;
dout45m,dout45b:
outstd_logic_vector（7downto0））;
endentityt45s;
architectureartoft45sis
signalt6b:
std_logic_vector（5downto0）;
begin
process（sb,clk,en45）is
begin
ifsb='0'thent6b<=t6b-t6b-1;
elsif（clk'eventandclk='1'）then
ifen45='1'thent6b<=t6b+1;
elsifen45='0'thent6b<=t6b-t6b-1;
endif;
endif;
endprocess;
process（t6b）is
begin
caset6bis
when"000000"=>dout45m<="01000101";dout45b<="01010000";
when"000001"=>dout45m<="01000100";dout45b<="01001001";
when"000010"=>dout45m<="01000011";dout45b<="01001000";
when"000011"=>dout45m<="01000010";dout45b<="01000111";
when"000100"=>dout45m<="01000001";dout45b<="01000110";
when"000101"=>dout45m<="01000000";dout45b<="01000101";
when"000110"=>dout45m<="00111001";dout45b<="01000100";
when"000111"=>dout45m<="00111000";dout45b<="01000011";
when"001000"=>dout45m<="00110111";dout45b<="01000010";
when"001001"=>dout45m<="00110110";dout45b<="01000001";
when"001010"=>dout45m<="00110101";dout45b<="01000000";
when"001011"=>dout45m<="00110100";dout45b<="01101001";
when"001100"=>dout45m<="00110011";dout45b<="00111000";
when"001101"=>dout45m<="00110010";dout45b<="00110111";
when"001110"=>dout45m<="00110001";dout45b<="00110110";
when"001111"=>dout45m<="00110000";dout45b<="00110101";
when"010000"=>dout45m<="00101001";dout45b<="00110100";
when"010001"=>dout45m<="00101000";dout45b<="00110011";
when"010010"=>dout45m<="00100111";dout45b<="00110010";
when"010011"=>dout45m<="00100110";dout45b<="00110001";
when"010100"=>dout45m<="00100101";dout45b<="00110000";
when"010101"=>dout45m<="00100100";dout45b<="00101001";
when"010110"=>dout45m<="00100011";dout45b<="00101000";
when"010111"=>dout45m<="00100010";dout45b<="00100111";
when"011000"=>dout45m<="00100001";dout45b<="00100110";
when"011001"=>dout45m<="00100000";dout45b<="00100101";
when"011010"=>dout45m<="00011001";dout45b<="00100100";
when"011011"=>dout45m<="00011000";dout45b<="00100011";
when"011100"=>dout45m<="00010111";dout45b<="00100010";
when"011101"=>dout45m<="00010110";dout45b<="00100001";
when"011110"=>dout45m<="00010101";dout45b<="00100000";
when"011111"=>dout45m<="00010100";dout45b<="00011001";
when"100000"=>dout45m<="00010011";dout45b<="00011000";
when"100001"=>dout45m<="00010010";dout45b<="00010111";
when"100010"=>dout45m<="00010001";dout45b<="00010110";
when"100011"=>dout45m<="00010000";dout45b<="00010101";
when"100100"=>dout45m<="00001001";dout45b<="00010100";
when"100101"=>dout45m<="00001000";dout45b<="00010011";
when"100110"=>dout45m<="00000111";dout45b<="00010010";
when"100111"=>dout45m<="00000110";dout45b<="00010001";
when"101000"=>dout45m<="00000101";dout45b<="00010000";
when"101001"=>dout45m<="00000100";dout45b<="00001001";
when"101010"=>dout45m<="00000011";dout45b<="00001000";
when"101011"=>dout45m<="00000010";dout45b<="00000111";
when"101100"=>dout45m<="00000001";dout45b<="00000110";
whenothers=>dout45m<="00000000";dout45b<="00000000";
endcase;
endprocess;
endarchitectureart;
（4）t05s.vhd
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityt05sis
port（clk,en05m,en05b:
instd_logic;
dout5:
outstd_logic_vector（7downto0））;
endentityt05s;
architectureartoft05sis
signalt3b:
std_logic_vector（2downto0）;
begin
process（clk,en05m,en05b）is
begin
if（clk'eventandclk='1'）then
ifen05m='1'thent3b<=t3b+1;
elsifen05b='1'thent3b<=t3b+1;
elsifen05b='0'thent3b<=t3b-t3b-1;
endif;
endif;
endprocess;
process（t3b）is
begin
caset3bis
when"000"=>dout5<="00000101";
when"001"=>dout5<="00000100";
when"010"=>dout5<="00000011";
when"011"=>dout5<="00000010";
when"100"=>dout5<="00000001";
whenothers=>dout5<="00000000";
endcase;
endprocess;
endarchitectureart;
（5）—t25s.vhd
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityt25sis
port（sb,sm,clk,en25:
instd_logic;
dout25m,dout25b:
outstd_logic_vector（7downto0））;
endentityt25s;
architectureartoft25sis
signalt5b:
std_logic_vector（4downto0）;
begin
process（sb,sm,clk,en25）is
begin
ifsb='0'thent5b<=t5b-t5b-1;
elsifsm='0'thent5b<=t5b-t5b-1;
elsif（clk'eventandclk='1'）then
ifen25='1'thent5b<=t5b+1;
elsifen25='0'thent5b<=t5b-t5b-1;
endif;
endif;
endprocess;
process（t5b）is
begin
caset5bis
when"00000"=>dout25b<="00100101";dout25m<="00110000";
when"00001"=>dout25b<="00100100";dout25m<="00101001";
when"00010"=>dout25b<="00100011";dout25m<="00101000";
when"00011"=>dout25b<="00100010";dout25m<="00100111";
when"00100"=>dout25b<="00100001";dout25m<="00100110";
when"00101"=>dout25b<="00100000";dout25m<="00100101";
when"00110"=>dout25b<="00011001";dout25m<="00100100";
when"00111"=>dout25b<="00011000";dout25m<="00100011";
when"01000"=>dout25b<="00010111";dout25m<="00100010";
when"01001"=>dout25b<="00010110";dout25m<="00100001";
when"01010"=>dout25b<="00010101";dout25m<="00100000";
when"01011"=>dout25b<="00010100";dout25m<="00011001";
when"01100"=>dout25b<="00010011";dout25m<="00011000";
when"01101"=>dout25b<="00010010";dout25m<="00010111";
when"01110"=>dout25b<="00010001";dout25m<="00010110";
when"01111"=>dout25b<="00010000";dout25m<="00010101";
when"10000"=>dout25b<="00001001";dout25m<="00010100";
when"10001"=>dout25b<="00001000";dout25m<="00010011";
when"10010"=>dout25b<="00000111";dout25m<="00010010";
when"10011"=>dout25b<="00000110";dout25m<="00010001";
when"10100"=>dout25b<="00000101";dout25m<="00010000";
when"10101"=>dout25b<="00000100";dout25m<="00010001";
when"10110"=>dout25b<="00000011";dout25m<="00001000";
when"10111"=>dout25b<="00000010";dout25m<="00000111";
when"11000"=>dout25b<="00000001";dout25m<="00000110";
whenothers=>dout25b<="00000000";dout25m<="00000000";
endcase;
endprocess;
endarchitectureart;
（6）—xskz.vhd
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityxskzis
port（en45,en25,en05m,en05b:
instd_logic;
ain45m,ain45b,ain25m,ain25b,ain05:
instd_logic_vector（7downto0）;
doutm,doutb:
outstd_logic_vector（7downto0））;
endentityxskz;
architectureartofxskzis
begin
process（en45,en25,en05m,en05b,ain45m,ain45b,ain25m,ain25b,ain05）is
begin
ifen45='1'thendoutm<=ain45m（7downto0）;doutb<=ain45b（7downto0）;
elsifen05m='1'thendoutm<=ain05（7downto0）;doutb<=ain05（7downto0）;
elsifen25='1'thendoutm<=ain25m（7downto0）;doutb<=ain25b（7downto0）;
elsifen05b='1'thendoutm<=ain05（7downto0）;doutb<=ain05（7downto0）;
endif;
endprocess;
endarchitectureart;
（7）—ymq.vhd
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityymqis
port（clk:
instd_logic;
ain41,ain42,ain43,ain44:
instd_logic_vector（3downto0）;
del:
outstd_logic_vector（2downto0）;
dout7:
outstd_logic_vector（6downto0））;
endentityymq;
architectureartofymqis
signalain4:
std_logic_vector（3downt
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