EDA 电子钟.docx

EDA 电子钟.docx

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EDA电子钟

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entitycon60vis------定义六十进制计数器（分,秒port（clk:

instd_logic;

en:

instd_logic;

clr:

instd_logic;

ld:

instd_logic;

d:

instd_logic_vector（7downto0;

co:

outstd_logic;

qh:

bufferstd_logic_vector（3downto0;

ql:

bufferstd_logic_vector（3downto0;

endcon60v;

architecturebhvofcon60vis

begin

co<='1'when（qh="0101"andql="1001"anden='1'else'0';

process（clk,clr,ld

begin

if（clr='0'then

qh<="0000";

ql<="0000";

elsif（clk'eventandclk='1'then

if（ld='0'then

qh<=d（7downto4;

ql<=d（3downto0;

elsif（en='1'then

if（ql<9thenql<=ql+1;

elseql<="0000";

if（qh<5thenqh<=qh+1;

elseqh<="0000";

endif;

endif;

endif;

endif;

endprocess;

endbhv;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_unsigned.all;

entitycon24vis

port（clk:

instd_logic;

clr:

std_logic;

ld:

instd_logic;

d:

instd_logic_vector（7downto0;

co:

outstd_logic;

qh:

bufferstd_logic_vector（3downto0;

ql:

bufferstd_logic_vector（3downto0;

endcon24v;

architecturebhvofcon24vis

begin

co<='1'when（qh="0000"andql="0011"anden='1'else'0';

process（clk,clr,ld

begin

if（clr='0'then

qh<="0000";

ql<="0000";

elsif（clk'eventandclk='1'then

if（ld='0'then

qh<=d（7downto4;

ql<=d（3downto0;

elsif（en='1'then

if（qh="0010"andql="0011"then

qh<="0000";ql<="0000";

elseql<=ql+1;

if（ql<9thenql<=ql+1;

elseql<="0000";

if（qh<2thenqh<=qh+1;

elseqh<="0000";

endif;

endif;

endif;

endif;

endif;

endprocess;

endbhv;

libraryieee;

useieee.std_logic_1164.all;

entitydianzibiaois------定义电子表可以实现功能port（day:

outstd_logic;

clr,en,ld,clk:

instd_logic;

d:

instd_logic_vector（7downto0;

miao0:

bufferstd_logic_vector（3downto0;

miao1:

bufferstd_logic_vector（3downto0;

fen0:

bufferstd_logic_vector（3downto0;

fen1:

bufferstd_logic_vector（3downto0;

shi0:

bufferstd_logic_vector（3downto0;

shi1:

bufferstd_logic_vector（3downto0;

enddianzibiao;

architectureoneofdianzibiaois---------------------电子表包含六十和十二进制的计数功能

componentcon60v-------元件例化语句调用六十进制计数器

port（

clk:

instd_logic;

en:

instd_logic;

clr:

instd_logic;

ld:

instd_logic;

d:

instd_logic_vector（7downto0;

co:

outstd_logic;

qh:

bufferstd_logic_vector（3downto0;

ql:

bufferstd_logic_vector（3downto0;

endcomponent;

componentcon24v-------元件例化语句调用萍剖?

port（clk:

instd_logic;

en:

instd_logic;

clr:

std_logic;

ld:

instd_logic;

d:

instd_logic_vector（7downto0;

co:

outstd_logic;

qh:

bufferstd_logic_vector（3downto0;

ql:

bufferstd_logic_vector（3downto0;

ENDcomponent;

signalmiaojinwei,fenjinwei:

std_logic;

begin

u1:

con60vportmap（qh=>miao1,ql=>miao0,co=>miaojinwei,clk=>clk,clr=>clr,en=>en,ld=>ld,d=>d;

u2:

con60vportmap（clk=>miaojinwei,qh=>fen1,ql=>fen0,co=>fenjinwei,clr=>clr,en=>en,ld=>ld,d=>d;

u3:

con24vportmap（CLK=>fenjinwei,qh=>shi1,ql=>shi0,clr=>clr,en=>en,ld=>ld,d=>d,co=>day;

endone;

libraryieee;

useieee.std_logic_1164.all;

useieee.std_logic_arith.all;

useieee.std_logic_unsigned.all;

entityyimaqiis-------定义一个译码器

port

（

num:

instd_logic_vector（3downto0;

co:

outstd_logic_vector（6downto0;

endyimaqi;

architectureoneofyimaqiis

begin

withnumselect

co<="1111110"when"0000",

"0110000"when"0001",

"1101101"when"0010",

"1111001"when"0011",

"0110011"when"0100",

"1011011"when"0101",

"1011111"when"0110",

"1110000"when"0111",

"1111111"when"1000",

"1111011"when"1001",

"0000000"whenothers;

endarchitectureone;

libraryieee;

useieee.std_logic_1164.all;

entitydianzibiaoshixianis----------定义可以使用的电子表

port（

clr,en,ld,clk:

instd_logic;

d:

instd_logic_vector（7downto0;

miao0:

bufferstd_logic_vector（6downto0;

miao1:

bufferstd_logic_vector（6downto0;

fen0:

bufferstd_logic_vector（6downto0;

fen1:

bufferstd_logic_vector（6downto0;

shi0:

bufferstd_logic_vector（6downto0;

shi1:

bufferstd_logic_vector（6downto0;

enddianzibiaoshixian;

architectureoneofdianzibiaoshixianis

componentdianzibiao----------调用实现功能的电子表

port（day:

outstd_logic;

clr,en,ld,clk:

instd_logic;

d:

instd_logic_vector（7downto0;

miao0:

bufferstd_logic_vector（3downto0;

miao1:

bufferstd_logic_vector（3downto0;

fen0:

bufferstd_logic_vector（3downto0;

fen1:

bufferstd_logic_vector（3downto0;

shi0:

bufferstd_logic_vector（3downto0;

shi1:

bufferstd_logic_vector（3downto0;

ENDcomponent;

componentyimaqi-----------调用译码器

port

（

num:

instd_logic_vector（3downto0;

co:

outstd_logic_vector（6downto0;

ENDcomponent;

signala,b,c,m,e,f:

std_logic_vector（3downto0;

begin

u1:

dianzibiaoportmap（clr=>clr,en=>en,ld=>ld,clk=>clk,d=>d,miao0=>a,miao1=>b,fen0=>c,fen1=>m,shi0=>e,shi1=>f;

u2:

yimaqiportmap（num=>a,co=>miao0;

u3:

yimaqiportmap（num=>b,co=>miao1;

u4:

yimaqiportmap（num=>c,co=>fen0;

u5:

yimaqiportmap（num=>m,co=>fen1;

u6:

yimaqiportmap（num=>e,co=>shi0;

u7:

yimaqiportmap（num=>f,co=>shi1;

endone;