ARM汇编语言程序设计总结.docx
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ARM汇编语言程序设计总结
ARM汇编语言程序设计总结
一、常用指令
1．存储器访问指令
LDR
STR
LDR
Load32-bitword toMemory.
Syntax LDR{cond}Rd,[Rn]
LDR{cond}Rd,[Rn,offset]
LDR{cond}Rd,[Rn,offset]!
LDR{cond}Rd,label
LDR{cond}Rd,[Rn],offset
Description LDR{cond}Rd,[Rn]（zerooffset）
Rnisusedasaddressvalue.
LDR{cond}Rd,[Rn,offset]（Pre-indexedoffset）
Rnandoffsetareaddedandusedasaddressvalue.
LDR{cond}Rd,[Rn,offset]{!
}（Pre-indexedoffsetwithupdate）
Rnandoffsetareaddedandusedasaddressvalue.ThenewaddressvalueiswrittentoRn.
LDR{cond}Rd,label（Program-relative）
TheassemblercalculatesthePCoffsetandgeneratesLDR{cond}Rd,[R15,offset].
LDR{cond}Rd,[Rn],offset（Post-indexedoffset）
Rnisusedasaddressvalue.Aftermemorytransfer,theoffsetisaddedtoRn.
Example
LDRR8,[R10]//loadsr8fromtheaddressinr10.
LDRNER2,[R5,#960]!
//（conditionally）loadsr2fromaword960bytesabovetheaddressinr5,andincrementsr5by960.
LDRR0,localdata//loadsawordlocatedatlabellocaldata
STR
Storeregister32-bitwordstoMemory.Theaddressmustbe32-bitword-aligned.
Syntax STR{cond}Rd,[Rn]
STR{cond}Rd,[Rn,offset]
STR{cond}Rd,[Rn,offset]!
STR{cond}Rd,label
STR{cond}Rd,[Rn],offset
Description STR{cond}Rd,[Rn]（zerooffset）
Rnisusedasaddressvalue.
STR{cond}Rd,[Rn,offset]（Pre-indexedoffset）
Rnandoffsetareaddedandusedasaddressvalue.
STR{cond}Rd,[Rn,offset]!
（Pre-indexedoffsetwithupdate）
Rnandoffsetareaddedandusedasaddressvalue.ThenewaddressvalueiswrittentoRn.
STR{cond}Rd,label（Program-relative）
TheassemblercalculatesthePCoffsetandgeneratesSTR{cond}Rd,[R15],offset.
STR{cond}Rd,[Rn],offset（Post-indexedoffset）
Rnisusedasaddressvalue.Aftermemorytransfer,theoffsetisaddedtoRn.
ExampleLDRr8,[r10]//loadsr8fromtheaddressinr10.
LDRNEr2,[r5,#960]!
//（conditionally）loadsr2fromaword
//960bytesabovetheaddressinr5,and
//incrementsr5by960.
STRr2,[r9,#consta-struc]//consta-strucisanexpressionevaluating
//toaconstantintherange0-4095.
STRBr0,[r3,-r8,ASR#2]//storestheleastsignificantbytefrom
//r0toabyteatanaddressequalto
//contents（r3）minuscontents（r9）/4.
//r3andr8arenotaltered.
STRr5,[r7],#-8//storesawordfromr5totheaddress
//inr7,andthendecrementsr7by8.
LDRr0,localdata//loadsawordlocatedatlabellocaldata
2．一般数据处理指令
ADDSUBADCSBC
AND,ORR,EOR,
CMPTST
UMULL,UMLAL,SMULL,andSMLAL
MUL,MLA,andMLS
ADC
AddwithCarry.
SyntaxADC{cond}{S} Rd,Rn,Op2
DescriptionAddRnandOp2andCarryflagandstoreresulttoRd.ADCistypicalusedformulti-wordarithmetic.
ConditionFlagsIfSisspecifiedupdateflags:
N,Z,C,V.
Example
ADDSR0,R2,R4//addR2+R4,storeresulttoR0,setflags
ADCR1,R3,R5//addR3+R5withcarryfrompreviousADDS,storeresulttoR1
ADD
Addvaluesandstoreresulttoregister.
Syntax ADD{cond}{S} Rd,Rn,Op2
Description AddRnandOp2andstoreresulttoRd.
ConditionFlags IfSisspecifiedupdateflags:
N,Z,C,V.
Example
ADDSR0,R2,R4//AddR2andR4andstoreresulttoR0,updateflags
ADDR4,R4,#0xFF00//Addvaluein0xFF00andR4andstoreresultinR4
SUB
Subtractregisters.
SyntaxSUB{cond}{S} Rd,Rn,Op2
DescriptionsubtractsthevalueofOp2fromthevalueinRn.
ConditionFlagsIfSisspecifiedupdateflags:
N,Z,C,V.
ExampleSUBSR8,R6,#240//R8=R6-240
SBC
Subtractwithcarry.
Syntax SBC{cond}{S} Rd,Rn,Op2
Description synthesizemultiwordarithmetic.
ConditionFlags IfSisspecifiedupdateflags:
N,Z,C,V.
ExampleADDSR0,R2,R4
ADDR4,R4,#0xFF00
AND
LogicalANDoperation.
Syntax AND{cond}{S} Rd,Rn,Op2
Description LoadRdwithlogicalANDofRnwithOp2.Rd:
=RnANDOp2
ConditionFlags IfSisspecified,N,Zflagsareupdated.CflagmaybeupdatedbycalculationofOp2.
Example
ANDR9,R2,#0xFF00//LoadR9withR2andvaluein0xFF00
ORR
LogicalORoperation.
Syntax ORR{cond}{S} Rd,Rn,Op2
Description ORoperationsonthevaluesinRnandOp2.
ConditionFlags IfSisspecified,N,Zflagsareupdated.CflagmaybeupdatedbycalculationofOp2.
ExampleORRR2,R0,R5//Rd=R0orR5
CMP
Compare.Usedincombinationwithconditionalbranchinstructions.
SyntaxCMP{cond}Rn,Op2
DescriptionsubtractsthevalueofOp2fromthevalueinRn （equalstotheSUBSinstructionwithadiscardedresult）.
Thisinstructionupdatestheconditionflags,butdonotplacearesultinaregister.
ConditionFlagsN,Z,CandVflagsareupdated.
ExampleCMPR2,R9//SubtractvalueofR9fromR2
TST
Test.
SyntaxTST{cond}Rn,Op2
DescriptionperformsabitwiseANDoperationonthevalueinRnandthevalueofOp2.ThisissimilartotheANDSinstruction,exceptthattheresultisdiscarded.
ConditionFlagsNandZflagsareupdatedaccordingtheresult.CflagmaybeupdatedduringthecalculationofOp2.
ExampleTSTNEr1,r5,ASRr1
MUL
Multiply（32-bitby32-bit,bottom32-bitresult）.
Syntax MUL{cond}{S}Rd,Rm,Rs
Description multipliesthevaluesfromRmandRs,andplacestheleastsignificant32bitsoftheresultinRd.
ConditionFlags IfSisspecified:
▪NandZflagsaccordingtotheresult.
▪theCflaginARMarchitecturev4andearlierwillbecorrupted.
▪theCflaginARMarchitecturev5andlaterisnotaffected.
ExampleMULR10,R2,R5//R10:
=R2*R5
3．分支控制指令
B,BL,BX,BLX,andBXJ
B
Branchtolabel.Usedtojumptoaspecificprogramlocation.
Syntax B{cond}label
Description Thejumpdistancemustbewithin-252to+258bytesforconditionaland±2KBytesforunconditionalbranch.
ConditionFlags notmodified.
ExampleCMPR1,#10//compareR10with#10
BEQval_ok//jumptolabelval_ok
val_ok:
val_err:
Bval_err//jumptoitself（loopforever）
BL
BranchwithLink.Usetocallsubroutines.
Syntax BL{cond}label
Description CopyaddressofnextinstructiontoR14andjumptolabel.Thejumpdistancemustbewithin±4Mbofthecurrentinstruction.Notethatthismnemonicisgeneratedastwo16-bitThumbinstructions.
ConditionFlags notmodified.
ExampleBLsub+ROM//Callsubroutineatcomputedaddress
ADDSR1,#1//Add1toregister1,settingCPSRflagsontheresultthencallsubroutineiftheCflagisclear,wichwillbethecase
//unlessR1held0xFFFFFFFF
BX
BranchindirectandswitchCPUmode（Thumb/ARM）asrequired.
Syntax BX{cond}Rm
Description BranchtoaddressinRm.ChangetoARMmodeifbit0ofRmisclear.
ConditionFlags notmodified.
ExampleBXR5//branchindirecttoaddressfunction
4.ARM伪指令
1.符号定义伪指令
GBLA,GBLL,andGBLS
LCLA,LCLL,andLCLS
2.数据定义伪指令
DCB
DCDandDCDU
5.条件代码
ConditionCode
MostARMinstructionsandtheThumbBranchinstructionincludeaconditioncodefield.ThisfieldismarkedintheCPUinstructionswith{cond}.
AconditionalinstructionisonlyexecutedonmatchoftheconditionflagsintheProgramStatusRegister.Forexample,theBEQ（BinstructionwithEQcondition）branchesonlyiftheZflagisset.Ifthe{cond}fieldisemptytheinstructionisalwaysexecuted.
{cond}Suffix
TestedStatusFlags
Description
EQ
Zset
equal
NE
Zclear
notequal
CS/HS
Cset
unsignedhigherorsame
CC/LO
Cclear
unsignedlower
MI
Nset
negative
PL
Nclear
positiveorzero
VS
Vset
overflow
VC
Vclear
nooverflow
HI
CsetandZclear
unsignedhigher
LS
CclearorZset
unsignedlowerorsame
GE
NequalsV
signedgreaterorequal
LT
NnotequaltoV
signedlessthan
GT
ZclearAND（NequalsV）
signedgreaterthan
LE
ZsetOR（NnotequaltoV）
signedlessthanorequal
AL
（ignored）
always（usuallyomitted）
Examples:
CMPR5,#10//compareR5with10
BHIlab1//branchtolab1ifvalueinR5ishigherthan10
:
lab1:
TSTR5,#10//testcontentofR5against10
ADDEQR6,#40//add40toR6ifR5contains10
6.移位类型
TheARMCPUhasverypowerfulshiftoperationsthatcanbeusedtogetherwithstandardCPUinstructions.Thevariousshifttypesareexplainedbelow:
LogicalShiftRight（LSR）
LogicalshiftrightisencodedwithLSR#norLSRRsintheOp2field.Thevalue0isshiftedintobit31andtheCarryflag（C）holdsthelastbitshiftedout.
LogicalShiftLeft（LSL）
LogicalshiftleftisencodedwithLSL#norLSLRsintheOp2field.Thevalue0isshiftedintobit0andtheCarryflag（C）holdsthelastbitshiftedout.
ArithmeticShiftRight（ASR）
ArithmeticshiftrightisencodedwithASR#norASRRsintheOp2field.Thesignbit（bit31ofvalue）isshiftedintothehighbit31andtheCarryflag（C）holdsthelastbitshiftedout.
RotateRight（ROR）
RotaterightisencodedwithROR#nintheOp2field.Bit0ofthevalueisshiftedintobit31.TheCarryflag（C）holdsthelastbitshiftedout.
RotateRightExtended（RRX）
RotaterightextendedisencodedwithRRXintheOp2field.ThevalueoftheCarryflag（C）isshiftedintobit31.Theshiftedoutbit0iswrittentoC.
Binaryoperators
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3.6.11. Binaryoperators
Binaryoperatorsarewrittenbetweenthepairofsubexpressionstheyoperateon.
Binaryoperatorshavelowerprecedencethanunaryoperators.Binaryoperatorsappearinthissectioninorderofprecedence.
Note
TheorderofprecedenceisnotthesameasinC,seeOperatorprecedenceinarmasmandC.
Multiplicativeoperators
Multiplicativeoperatorshavethehighestprecedenceofallbinaryoperators.Theyactonlyonnumericexpressions.
Table 3.9showsthemultiplicativeoperators.
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