八位二进制频率计设计.docx
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八位二进制频率计设计
一、课程设计题目
8位十进制频率计设计
二、课程设计目的
1.设计8位十进制频率计设计。
2.学习较复杂的数字系统设计方法。
3.学习巩固VHDL元件例化语句的使用。
4.熟练掌握和应用QUARTUS软件的使用。
5.学习和使用AltreaDE2-115实验箱。
6.巩固和加深对“EDA技术”、“数字电子技术”的基本知识的理解。
三、课程设计所用器材
1、装有QuartusII软件的计算机一台。
2、芯片:
使用altera公司生产的EP4CE115F29C7。
3、EDA实验箱套装一套。
四、设计原理
根据频率的定义和频率测量的基本原理,测定信号的频率必须有一个脉宽为1秒的对输入信号脉冲计数允许的信号;1秒计数结束后,计数值锁入锁存器的锁存信号和为下一测频计数周期作准备的计数器清0信号。
这清0个信号可以由一个测频控制信号发生器TESTCTL产生,它的设计要求是,TESTCTL的计数使能信号CNT_EN能产生一个1秒脉宽的周期信号,并对频率计的每一计数器CNT10的EN使能端进行同步控制。
当CNT_EN高电平时,允许计数;低电平时停止计数,并保持其所计的脉冲数。
在停止计数期间,首先需要一个锁存信号LOAD的上跳沿将计数器在前1秒钟的计数值锁存进各锁存器REG4B中,并由外部的7段译码器译出,显示计数值。
设置锁存器的好处是,显示的数据稳定,不会由于周期性的清零信号而不断闪烁。
锁存信号之后,必须有一清零信号RST_CNT对计数器进行清零,为下1秒钟的计数操作作准备。
图
(1)原理图
五、功能模块
1、分频模块
1)五分频器:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityDIV5is
port(clkk:
instd_logic;
k_or,k1,k2:
outstd_logic
);
endentityDIV5;
architecturebhvofDIV5is
signalc1,c2:
std_logic_vector(2downto0);
signalm1,m2:
std_logic;
begin
process(clkk,c1)begin
ifrising_edge(clkk)then
if(c1="100")thenc1<="000";
elsec1<=c1+1;
endif;
if(c1="001")thenm1<=notm1;
elsif(c1="011")thenm1<=notm1;
endif;
endif;
endprocess;
process(clkk,c2)begin
iffalling_edge(clkk)then
if(c2="100")thenc2<="000";
elsec2<=c2+1;
endif;
if(c2="001")thenm2<=notm2;
elsif(c2="011")thenm2<=notm2;
endif;
endif;
endprocess;
k1<=m1;k2<=m2;k_or<=m1orm2;
endarchitecturebhv;
2)十分频器:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityDIV10is
port(clkk:
instd_logic;
k:
outstd_logic
);
endentityDIV10;
architecturebhvofDIV10is
signals:
std_logic;
signalc:
std_logic_vector(3downto0);
begin
process(clkk,c)begin
ifrising_edge(clkk)then
if(c="1001")thenc<="0000";
elsec<=c+1;
endif;
if(c="0101")thens<=nots;
elsif(c="0000")thens<=nots;
endif;
endif;
endprocess;
k<=s;
endarchitecturebhv;
2、四选一多路选择器:
libraryieee;
useieee.std_logic_1164.all;
entityMUX41Ais
port(a,b,c,d,s0,s1:
instd_logic;
y:
outstd_logic
);
endentityMUX41A;
architecturebhvofMUX41Ais
signals:
std_logic_vector(1downto0);
begin
s<=s1&s0;
process(s1,s0)
begin
case(s)is
when"00"=>y<=a;
when"01"=>y<=b;
when"10"=>y<=c;
when"11"=>y<=d;
whenothers=>NULL;
endcase;
endprocess;
endarchitecturebhv;
3、控制模块:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityTESTCTLis
port(clk:
instd_logic;
clr:
outstd_logic;
load:
outstd_logic;
ena:
outstd_logic
);
endentityTESTCTL;
architecturebhvofTESTCTLis
signalDiv2CLK:
std_logic;
begin
process(clk)begin
ifclk'eventandclk='1'then
Div2CLK<=notDiv2CLK;
endif;
endprocess;
process(clk,Div2CLK)
begin
ifclk='0'andDiv2CLK='0'thenclr<='1';
elseclr<='0';
endif;
endprocess;
load<=notDiv2CLK;
ena<=Div2CLK;
endarchitecturebhv;
4、计数模块
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityCNT10is
port(fin:
instd_logic;
clr:
instd_logic;
ena:
instd_logic;
cout:
outstd_logic;
dout:
outstd_logic_vector(3downto0)
);
endentityCNT10;
architecturebhvofCNT10is
begin
process(fin,clr,ena)
variableq:
std_logic_vector(3downto0);
begin
ifclr='1'thenq:
="0000";
elsiffin'eventandfin='1'then
ifena='1'then
ifq<9thenq:
=q+1;
elseq:
="0000";
endif;
endif;
endif;
ifq="1001"thencout<='1';
elsecout<='0';
endif;
dout<=q;
endprocess;
endarchitecturebhv;
5、译码模块
libraryieee;
useieee.std_logic_1164.all;
entityDECL7Sis
port(A:
instd_logic_vector(3downto0);
LED7S:
outstd_logic_vector(6downto0)
);
end;
architecturebhvofDECL7Sis
begin
process(A)begin
caseAis
when"0000"=>LED7S<="1000000";
when"0001"=>LED7S<="1111001";
when"0010"=>LED7S<="0100100";
when"0011"=>LED7S<="0110000";
when"0100"=>LED7S<="0011001";
when"0101"=>LED7S<="0010010";
when"0110"=>LED7S<="0000010";
when"0111"=>LED7S<="1111000";
when"1000"=>LED7S<="0000000";
when"1001"=>LED7S<="0010000";
when"1010"=>LED7S<="0001000";
when"1011"=>LED7S<="0000011";
when"1100"=>LED7S<="1000110";
when"1101"=>LED7S<="0100001";
when"1110"=>LED7S<="0000110";
when"1111"=>LED7S<="0001110";
whenothers=>NULL;
endcase;
endprocess;
end;
6、锁存模块:
libraryieee;
useieee.std_logic_unsigned.all;
useieee.std_logic_1164.all;
entityREG32Bis
port(load:
instd_logic;
din:
instd_logic_vector(31downto0);
fout:
outstd_logic_vector(31downto0)
);
endentityREG32B;
architecturebhvofREG32Bis
begin
process(load,din)
begin
ifload'eventandload='1'
thenfout<=din;
endif;
endprocess;
endarchitecturebhv;
7、总电路例化程序:
libraryieee;
useieee.std_logic_1164.all;
entitykcsjis
port(clkk:
instd_logic;
fsin:
instd_logic;
key1,key2:
instd_logic;
qout:
outstd_logic_vector(55downto0)
);
endentitykcsj;
architecturebhvofkcsjis
componentTESTCTL
port(clk:
instd_logic;
clr:
outstd_logic;
load:
outstd_logic;
ena:
outstd_logic
);
endcomponent;
componentDIV5
port(clkk:
instd_logic;
k_or,k1,k2:
outstd_logic
);
endcomponent;
componentDIV10
port(clkk:
instd_logic;
k:
outstd_logic
);
endcomponent;
componentCNT10
port(fin:
instd_logic;
clr:
instd_logic;
ena:
instd_logic;
cout:
outstd_logic;
dout:
outstd_logic_vector(3downto0)
);
endcomponent;
componentREG32B
port(load:
instd_logic;
din:
instd_logic_vector(31downto0);
fout:
outstd_logic_vector(31downto0)
);
endcomponent;
componentMUX41A
port(a,b,c,d,s0,s1:
instd_logic;
y:
outstd_logic
);
endcomponent;
componentDECL7S
port(A:
instd_logic_vector(3downto0);
LED7S:
outstd_logic_vector(6downto0)
);
endcomponent;
signalnet1,net2,net3,net5:
std_logic;
signalnet4:
std_logic_vector(31downto0);
signala1,a2,a3,a4,a5,a6,a7,a8:
std_logic;
signalb1,b2,b3,b4,b5,b6,b7,b8:
std_logic_vector(3downto0);
signalc1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12:
std_logic;
signald1,d2,d3,d4,d5,d6,d7,d8:
std_logic_vector(3downto0);
begin
--1hz
u1:
DIV5portmap(clkk=>clkk,k_or=>c1);
u2:
DIV10portmap(clkk=>c1,k=>c2);
u3:
DIV10portmap(clkk=>c2,k=>c3);
u4:
DIV10portmap(clkk=>c3,k=>c4);
u5:
DIV10portmap(clkk=>c4,k=>c5);
u6:
DIV10portmap(clkk=>c5,k=>c6);
u7:
DIV10portmap(clkk=>c6,k=>c7);
u8:
DIV10portmap(clkk=>c7,k=>c8);
u9:
DIV5portmap(clkk=>fsin,k_or=>c9);--10mhz
u10:
DIV10portmap(clkk=>fsin,k=>c10);--5mhz
u11:
DIV10portmap(clkk=>c9,k=>c11);--1mhz
u12:
TESTCTLportmap(clk=>c8,load=>net1,
clr=>net2,ena=>net3);
u13:
MUX41Aportmap(a=>fsin,b=>c9,c=>c10,d=>c11,
s0=>key1,s1=>key2,y=>net5);
u14:
DECL7Sportmap(A=>d1,LED7S=>qout(6downto0));
u15:
DECL7Sportmap(A=>d2,LED7S=>qout(13downto7));
u16:
DECL7Sportmap(A=>d3,LED7S=>qout(20downto14));
u17:
DECL7Sportmap(A=>d4,LED7S=>qout(27downto21));
u18:
DECL7Sportmap(A=>d5,LED7S=>qout(34downto28));
u19:
DECL7Sportmap(A=>d6,LED7S=>qout(41downto35));
u20:
DECL7Sportmap(A=>d7,LED7S=>qout(48downto42));
u21:
DECL7Sportmap(A=>d8,LED7S=>qout(55downto49));
u22:
CNT10portmap(clr=>net2,ena=>net3,fin=>net5,
cout=>a1,dout=>b1);
u23:
CNT10portmap(clr=>net2,ena=>net3,fin=>a1,
cout=>a2,dout=>b2);
u24:
CNT10portmap(clr=>net2,ena=>net3,fin=>a2,
cout=>a3,dout=>b3);
u25:
CNT10portmap(clr=>net2,ena=>net3,fin=>a3,
cout=>a4,dout=>b4);
u26:
CNT10portmap(clr=>net2,ena=>net3,fin=>a4,
cout=>a5,dout=>b5);
u27:
CNT10portmap(clr=>net2,ena=>net3,fin=>a5,
cout=>a6,dout=>b6);
u28:
CNT10portmap(clr=>net2,ena=>net3,fin=>a6,
cout=>a7,dout=>b7);
u29:
CNT10portmap(clr=>net2,ena=>net3,fin=>a7,
dout=>b8);
u30:
REG32Bportmap(load=>net1,
din(3downto0)=>b1,
din(7downto4)=>b2,
din(11downto8)=>b3,
din(15downto12)=>b4,
din(19downto16)=>b5,
din(23downto20)=>b6,
din(27downto24)=>b7,
din(31downto28)=>b8,
fout(3downto0)=>d1,
fout(7downto4)=>d2,
fout(11downto8)=>d3,
fout(15downto12)=>d4,
fout(19downto16)=>d5,
fout(23downto20)=>d6,
fout(27downto24)=>d7,
fout(31downto28)=>d8);
endarchitecturebhv;
6、各功能模块仿真图
1、分频器
1)5分频
2)10分频
2、四选一多路选择器
3、控制器
4、计数器
5、译码器
6、锁存器
7、总电路RTL图
7、实验结果硬件显示图
1、程序加载完成示意图:
2、未经分频器的频率硬件图(50KHZ)
3、经5分频器的频率硬件图(10KHZ)
4、经10分频器的频率硬件图(5KHZ)
5、经50分频器的频率硬件图(1KHZ)
八、课程设计总结
9、参考文献
潘松、黄继业EDA技术实用教程------VerilogHDL版.北京:
科学出版社,2010.
潘松、黄继业数字电子技术基础【M】.北京:
科学出版社,2008.
乔庐峰.VerilogHDL数字系统设计与验证【M】.北京:
电子工业出版社,2009.
王金明.VerilogHDL数字系统设计与实践【M】.3版.北京:
电子工业出版社,2009.