C51的OBJ文件格式.docx

C51的OBJ文件格式.docx

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C51的OBJ文件格式

EXTERNALPRODUCTSPECIFICATION

FORTHE

MCS-51OBJECTMODULEFORMAT

V5.0

APPROVED

Sept.05,1982

TABLEOFCONTENTS

TABLEOFCONTENTS2

DISCLAIMER3

1PREFACE4

2OVERVIEWOF8051ARCHITECTURE4

2.1CodeSpace4

2.2ExternalDataSpace5

2.3InternalDataSpace5

2.3.1RegisterBanks6

2.3.2BitSpace6

2.3.3HardwareRegisters6

2.3.4Stack6

2.3.5AdditionalRAM（RUPI）6

2.3.6AddressingModes7

3REQUIREMENTS7

3.1RelocatableandExternalReferences7

3.2SegmentRelocation7

3.3IntermoduleLinkage8

3.4SymbolicDebugging9

3.5Compatibility9

3.6RUPI（AndotherMCS-51members）Support9

4OBJECTFILESTRUCTURE10

5RECORDFORMATS11

5.1Notation11

5.2ModuleHeaderRecord12

5.3ModuleEndRecord13

5.4DefinitionRecords13

5.4.1SegmentDefinitionsRecord13

5.4.2ExternalDefinitionsRecord17

5.5DebugRecords18

5.5.1ScopeDefinitionRecord18

5.5.2DebugItemsRecord20

5.6DataSection21

5.6.1ContentRecord22

5.6.2FixupRecord22

5.7LibraryRecords24

5.7.1LibraryHeaderRecord25

5.7.2LibraryModuleNamesRecord25

5.7.3LibraryModuleLocationsRecord25

5.7.4LibraryDictionaryRecord26

APPENDIXA:

RECORDFORMATSUMMARY27

APPENDIXB:

GLOSSARY28

APPENDIXC:

ABSOLUTEOBJECTMODULEFORMAT30

C.1StructureOfAbsoluteObjectFile30

C.2ModuleHeaderRecord30

C.3ModuleEndRecord31

C.4ScopeDefinitionRecord31

C.5DebugItemsRecord32

C.6ContentRecord34

APPENDIXD:

DOCUMENTHISTORY35

APPENDIXE:

REFERENCES36

DISCLAIMER

Intelmakesnorepresentationorwarrantieswithrespecttothecontentshereofandspecificallydisclaimsanyimpliedwarrantiesofmerchantabilityorfitnessforanyparticularpurpose.Further,IntelreservestherighttorevisethispublicationandtomakechangesfromtimetotimeinthecontenthereofwithoutobligationofInteltonotifyanypersonofsuchrevisionorchanges.ThepublicationofthisspecificationshouldnotbeconstruedasacommitmentonIntel'sparttoimplementanyproduct.

©1982IntelCorporation.Allrightsreserved.

DocumentControlCenterNumberforthisMCS-51OMFEPSis481984.

1PREFACE

Thedocumentdefinestheinternalformatoftherelocatableobjectfiles（ObjectModuleFormats,OMF）forthe8051family,producedbyIntel'slanguagetranslatorsandprocessedbyotherIntelsoftwareproducts.AppendixCdefinestheAbsoluteObjectModuleFormat（AOMF）whichisproducedbytheRL51program（andtheRASM,ifthesourceprogramisabsolute）.TheinformationinthisdocumentisnormallynotneededinordertouseIntelsoftware,butisprovidedforthepersonwhoneedstowriteprogramstoprocesstheseobjectfilesortocreatefilesinthesameformats.ThedesignisheavilybasedonthepreviousOMFsforthe8080andthe8086[1][2].

Chapter2coverssomebackgroundmaterialforthoseinterestedintherelevant8051architectureissuesandtheR&Lrequirementswhichledtothedefinitionoftheobjectfileformats.

Termswhichmayhavespecialmeaninginthedocumentaredescribedintheglossary（AppendixB）.

2OVERVIEWOF8051ARCHITECTURE

Thefollowingdiscussionoutlinesthoseaspectsofthe8051architecturerelevanttolinkingandlocating-thememorymodelandtheaddressingmodes.

Thememorymodelofthe8051familyconsistsofthreenon-overlappingaddressspaces-thecodespace,theexternaldataspaceandtheon-chipRAM.Somesectionsoftheon-chipRAMspaceservefunctionsinadditiontobeingtheusualrandomaccessbytestorage.Theseincludebit-addressablememory,andstack.

2.1CodeSpace

Thecodespacesizeis64Kbytes.Thelower4Kareon-chipROMandthetop60Kresidesinexternalmemorycomponents.Thelowerportionoftheon-chipROMcontainsaresetvector（atlocation0）and5interruptvectors（atlocations3,0BH,13H,1BHand23H）.

Thecodespaceusuallyconsistsofalltheprocedureandconstantsofaprogram.Itisassumedthatallthecodespace（off-chipaswell）consistsofROM.Consequentlyonlyreadoperationsareavailableondatainthecodespace.

Fourcodeaddressingmodesareprovided:

a.DirectAddressing-Thesecondandthirdbyteoftheinstructionformthefull16bitaddress（usedinjumpandcallinstructions）.Setupinstruction（MOVDPTR,code_address）.

b.Blockaddressing-Theinstructionprovidesthe11least-significantbitsoftheaddress.Theblockaddressisdefinedbythe5most-significantbitsoftheincrementedPC.Usedinjumpandcallinstructions.

c.RelativeAddressing-Theinstructionprovide8bitrelativeoffset.Usedinconditionaljumpsinarangeof+127/-128oftheincrementedPC.

d.IndirectAddressing-TheaddressiscomposedoftheDPTRorPCcontent,indexedbythe8bitaccumulator.

2.2ExternalDataSpace

TheExternalDataspacesizeis64Kbytes.Thisspaceiscompletelyexternaltothechip.Accessisprovidedviamoveinstructionswhichmovebytesbetweentheexternaldataspaceandtheaccumulator.

Twoexternaldataaddressingmodesareprovided:

a.IndirectDPTR-the16bitDPTRisusedtoaddressanylocationintheexternaldataspace.

b.IndirectRegister-R0orR1areusedtoaddressalocationwithina256bytepagedefinedbythecontentofthePort2register.

ThepointingregistersDPTR,R0andR1shouldbesetupbeforetheactualaccessisbeingmade.ThemachineprovideinstructionsforloadingtheDPTRwithaconstant（e.g.externaldataaddress）andincrementingit.Itprovidesmanyinstructionswhichload/manipulatethe8bitpointersR0andR1.

2.3InternalDataSpace

Theon-chipRAMspaceconsistsof128bytes（upto256bytesforafewmembersofthefamily,e.g.192fortheRUPI）ofdatamemoryand128bytesofmemorymappedhardwareregisters.Theon-chipRAMspaceisorganizedasfollows:

DIRECTADDRESSING

INDIRECTADDRESSING

256

HardwareRegisters

FutureAdditionalRAM

192

RUPIAdditionalRAM

128

FreeRAM

48

BitSpace

32

RegisterBank3

24

RegisterBank2

16

RegisterBank1

DefaultTOS

8

RegisterBank0

0

Thefunctionofthevariouscomponentsoftheon-chipRAMspaceandtheaddressingmodesbywhichtheymaybeaccessedarediscussedbelow.

2.3.1RegisterBanks

Thelower32bytesoftheon-chipRAMspacearedividedintofourregisterbanks,usuallyassociatedwithdifferentinterruptnestinglevels.Theeightregistersofthecurrentbank,selectedbytwobitswithinthePSW,areusuallyusedforscratchpadpurposes.

2.3.2BitSpace

Thebitspacecontain256individuallyaddressablebits.Bits0to127aremappedontobytes32to47oftheon-chipRAMspace.Bits128to255,someofwhicharenonexistent,aremappedontosomespecificregistersinthehardwarespace.OperationsonthebitspaceincludeSET,CLEAR,COMPLEMENT,AND,ORandTEST.

2.3.3HardwareRegisters

Whendirectaddressingisused,afew（20forthe8051,34fortheRUPI）ofthetop128bytesoftheon-chipRAMspacearemapped1-1ontoasetofhardwareregisters（A,B,DPTR,etc.）.ThusI/Oandotheraccessestothemachineitselfareaccomplishedbydirectmemoryoperations.Theresultofanaccesstoanunoccupiedlocationwithinthatsectionisundefined.

2.3.4Stack

ThetopofthestackisinitiallysetbyH/Wto07H（thestartofregisterbank1）butmayberelocatedtoanywhereelsewithintheon-chipRAMspacebysettingtheStackPointer（SP）.

Thestackgrowsupward,i.e.theSPisincrementedbeforeawriteoperation（PUSH/CALL/ACALLinstructions）andisdecrementedafterareadoperation（POP/RET/RETIinstructions）.

Thestackisbyteoriented.Howeverwhenusedincall/return-typeoperations,twobytes（afull16bitaddress）arepushed/popped.

2.3.5AdditionalRAM（RUPI）

Thereare64bytesofadditionalon-chipRAMavailableontheRUPIchip（locations128to191）.Othermembersofthefamilycanhaveupto128additionalon-chipRambytes.Theseadditionalbytescanonlybeaccessedintheindirectaddressingmode.Theymaybeusedasmemoryforthestack.

2.3.6AddressingModes

Theon-chipRAMspacecanbeaccessedusingthefollowingaddressingmodes:

a.DirectAddressing-thefull8bitaddressisgiveninthesecondbyteoftheinstruction.Addressesgreaterthen127accessthememorymappedhardwarespace.

b.IndirectRegisterAddressing-theaddressisspecifiedbythecontentofR0orR1.Addressesgreaterthen127addressnothingonthe8051andaddressesgreaterthen191addressnothingontheRUPI.

c.RegisterAddressing-athreebitfieldinthefirst（opcode）byteaddressesaregisterwithinthecurrentregisterbank.

d.BitAddressing-thisisadirectaddressingmodewherethefull（8-bit）bitaddressisgivenbythesecondbyteoftheinstruction.

e.Stackaddressing-See2.3.4.

3REQUIREMENTS

3.1RelocatableandExternalReferences

TheOMFshouldsupportrelocatableandexternalreferencesofthefollowingtypes:

a.LowByte-referencetothelow-orderbyteofanaddress.GeneratedbytheLOWoperatoror,fortheDATAandBITspaces,byadirect（full）addressreference.

b.HighByte-referencetothehigh-orderbyteofanaddress.GeneratedbytheHIGHoperator.ApplicabletoXDATAandCODEsegments.

c.FullCODE/XDATAAddress-afull16-bitreference.

d.InblockCODEAddress-an11-bitinblockreference.

e.RelativeCODEaddress-areference+127/-128relativetothePC（afteritwasincrementedtothenextinstruction）.

f.FullBitAddress-an8-bitbitaddress

g.MixedByte/BitAddress-an8-bitbitaddressofwhichonlythe（5-bit）byteaddresspartisrelocatable.

3.2SegmentRelocation

Theobjectcodewillbeorganizedinsegments.Thesegments,defined

bytheuserattranslationtime,willhavethefollowingattributes:

a.Name-obeystheusualrule