C51的OBJ文件格式.docx

1、C51的OBJ文件格式EXTERNAL PRODUCT SPECIFICATIONFOR THEMCS-51 OBJECT MODULE FORMATV5.0 APPROVED Sept. 05, 1982 TABLE OF CONTENTSTABLE OF CONTENTS 2DISCLAIMER 31 PREFACE 42 OVERVIEW OF 8051 ARCHITECTURE 42.1 Code Space 42.2 External Data Space 52.3 Internal Data Space 52.3.1 Register Banks 62.3.2 Bit Space

2、62.3.3 Hardware Registers 62.3.4 Stack 62.3.5 Additional RAM (RUPI) 62.3.6 Addressing Modes 73 REQUIREMENTS 73.1 Relocatable and External References 73.2 Segment Relocation 73.3 Intermodule Linkage 83.4 Symbolic Debugging 93.5 Compatibility 93.6 RUPI (And other MCS-51 members) Support 94 OBJECT FILE

3、 STRUCTURE 105 RECORD FORMATS 115.1 Notation 115.2 Module Header Record 125.3 Module End Record 135.4 Definition Records 135.4.1 Segment Definitions Record 135.4.2 External Definitions Record 175.5 Debug Records 185.5.1 Scope Definition Record 185.5.2 Debug Items Record 205.6 Data Section 215.6.1 Co

4、ntent Record 225.6.2 Fixup Record 225.7 Library Records 245.7.1 Library Header Record 255.7.2 Library Module Names Record 255.7.3 Library Module Locations Record 255.7.4 Library Dictionary Record 26APPENDIX A: RECORD FORMAT SUMMARY 27APPENDIX B: GLOSSARY 28APPENDIX C: ABSOLUTE OBJECT MODULE FORMAT 3

5、0C.1 Structure Of Absolute Object File 30C.2 Module Header Record 30C.3 Module End Record 31C.4 Scope Definition Record 31C.5 Debug Items Record 32C.6 Content Record 34APPENDIX D: DOCUMENT HISTORY 35APPENDIX E: REFERENCES 36DISCLAIMERIntel makes no representation or warranties with respect to the co

6、ntents hereof and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose. Further, Intel reserves the right to revise this publication and to make changes from time to time in the content hereof without obligation of Intel to notify any person of such

7、revision or changes. The publication of this specification should not be construed as a commitment on Intels part to implement any product. 1982 Intel Corporation. All rights reserved.Document Control Center Number for this MCS-51 OMF EPS is 481984.1 PREFACEThe document defines the internal format o

8、f the relocatable object files (Object Module Formats, OMF) for the 8051 family, produced by Intels language translators and processed by other Intel software products. Appendix C defines the Absolute Object Module Format (AOMF) which is produced by the RL51 program (and the RASM, if the source prog

9、ram is absolute). The information in this document is normally not needed in order to use Intel software, but is provided for the person who needs to write programs to process these object files or to create files in the same formats. The design is heavily based on the previous OMFs for the 8080 and

10、 the 8086 1 2.Chapter 2 covers some background material for those interested in the relevant 8051 architecture issues and the R&L requirements which led to the definition of the object file formats.Terms which may have special meaning in the document are described in the glossary (Appendix B).2 OVER

11、VIEW OF 8051 ARCHITECTUREThe following discussion outlines those aspects of the 8051 architecture relevant to linking and locating - the memory model and the addressing modes.The memory model of the 8051 family consists of three non-overlapping address spaces - the code space, the external data spac

12、e and the on-chip RAM. Some sections of the on-chip RAM space serve functions in addition to being the usual random access byte storage. These include bit-addressable memory, and stack.2.1 Code Space The code space size is 64K bytes. The lower 4K are on-chip ROM and the top 60K resides in external m

13、emory components. The lower portion of the on-chip ROM contains a reset vector (at location 0) and 5 interrupt vectors (at locations 3, 0BH, 13H, 1BH and 23H).The code space usually consists of all the procedure and constants of a program. It is assumed that all the code space (off-chip as well) con

14、sists of ROM. Consequently only read operations are available on data in the code space.Four code addressing modes are provided:a. Direct Addressing - The second and third byte of the instruction form the full 16 bit address (used in jump and call instructions). Setup instruction (MOV DPTR, code_add

15、ress).b. Block addressing - The instruction provides the 11 least-significant bits of the address. The block address is defined by the 5 most-significant bits of the incremented PC. Used in jump and call instructions.c. Relative Addressing - The instruction provide 8 bit relative offset. Used in con

16、ditional jumps in a range of +127/-128 of the incremented PC.d. Indirect Addressing - The address is composed of the DPTR or PC content, indexed by the 8 bit accumulator.2.2 External Data Space The External Data space size is 64K bytes. This space is completely external to the chip. Access is provid

17、ed via move instructions which move bytes between the external data space and the accumulator.Two external data addressing modes are provided:a. Indirect DPTR - the 16 bit DPTR is used to address any location in the external data space.b. Indirect Register - R0 or R1 are used to address a location w

18、ithin a 256 byte page defined by the content of the Port 2 register.The pointing registers DPTR, R0 and R1 should be set up before the actual access is being made. The machine provide instructions for loading the DPTR with a constant (e.g. external data address) and incrementing it. It provides many

19、 instructions which load/manipulate the 8 bit pointers R0 and R1.2.3 Internal Data SpaceThe on-chip RAM space consists of 128 bytes (up to 256 bytes for a few members of the family , e.g. 192 for the RUPI) of data memory and 128 bytes of memory mapped hardware registers. The on-chip RAM space is org

20、anized as follows: DIRECT ADDRESSINGINDIRECT ADDRESSING256Hardware RegistersFuture Additional RAM192RUPI Additional RAM128Free RAM48Bit Space32Register Bank 324Register Bank 216Register Bank 1Default TOS8Register Bank 00The function of the various components of the on-chip RAM space and the addressi

21、ng modes by which they may be accessed are discussed below.2.3.1 Register Banks The lower 32 bytes of the on-chip RAM space are divided into four register banks, usually associated with different interrupt nesting levels. The eight registers of the current bank, selected by two bits within the PSW,

22、are usually used for scratchpad purposes.2.3.2 Bit Space The bit space contain 256 individually addressable bits. Bits 0 to 127 are mapped onto bytes 32 to 47 of the on-chip RAM space. Bits 128 to 255, some of which are nonexistent, are mapped onto some specific registers in the hardware space. Oper

23、ations on the bit space include SET, CLEAR, COMPLEMENT, AND, OR and TEST.2.3.3 Hardware Registers When direct addressing is used, a few (20 for the 8051, 34 for the RUPI) of the top 128 bytes of the on-chip RAM space are mapped 1-1 onto a set of hardware registers (A, B, DPTR, etc.). Thus I/O and ot

24、her accesses to the machine itself are accomplished by direct memory operations. The result of an access to an unoccupied location within that section is undefined.2.3.4 Stack The top of the stack is initially set by H/W to 07H (the start of register bank 1) but may be relocated to anywhere else wit

25、hin the on-chip RAM space by setting the Stack Pointer (SP).The stack grows upward, i.e. the SP is incremented before a write operation (PUSH/CALL/ACALL instructions) and is decremented after a read operation (POP/RET/RETI instructions).The stack is byte oriented. However when used in call/return-ty

26、pe operations, two bytes (a full 16 bit address) are pushed/popped. 2.3.5 Additional RAM (RUPI) There are 64 bytes of additional on-chip RAM available on the RUPI chip (locations 128 to 191). Other members of the family can have up to 128 additional on-chip Ram bytes. These additional bytes can only

27、 be accessed in the indirect addressing mode. They may be used as memory for the stack.2.3.6 Addressing Modes The on-chip RAM space can be accessed using the following addressing modes:a. Direct Addressing - the full 8 bit address is given in the second byte of the instruction. Addresses greater the

28、n 127 access the memory mapped hardware space. b. Indirect Register Addressing - the address is specified by the content of R0 or R1. Addresses greater then 127 address nothing on the 8051 and addresses greater then 191 address nothing on the RUPI. c. Register Addressing - a three bit field in the f

29、irst (opcode) byte addresses a register within the current register bank.d. Bit Addressing - this is a direct addressing mode where the full (8-bit) bit address is given by the second byte of the instruction.e. Stack addressing - See 2.3.4.3 REQUIREMENTS 3.1 Relocatable and External References The O

30、MF should support relocatable and external references of the following types:a. Low Byte - reference to the low-order byte of an address. Generated by the LOW operator or, for the DATA and BIT spaces, by a direct (full) address reference. b. High Byte - reference to the high-order byte of an address

31、. Generated by the HIGH operator. Applicable to XDATA and CODE segments.c. Full CODE/XDATA Address - a full 16-bit reference.d. Inblock CODE Address - an 11-bit inblock reference.e. Relative CODE address - a reference +127/-128 relative to the PC (after it was incremented to the next instruction).f.

32、 Full Bit Address - an 8-bit bit address g. Mixed Byte/Bit Address - an 8-bit bit address of which only the (5-bit) byte address part is relocatable.3.2 Segment Relocation The object code will be organized in segments. The segments, defined by the user at translation time, will have the following attributes: a. Name - obeys the usual rule