实验一4位全加器的设计1.docx
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实验一4位全加器的设计1
实验一4位全加器的设计
一、实验目的:
1熟悉QuartusⅡ与ModelSim的使用;
2学会使用文本输入方式和原理图输入方式进行工程设计;
3分别使用行为和结构化描述方法进行四位全加器的设计;
4理解RTL视图和TechnologyMap视图的区别;
5掌握简单的testbench文件的编写。
二、实验原理:
一个4位全加器可以由4个一位全加器构成,加法器间的进位可以串行方式实现,即将低位加法器的进位输出cout与相邻的高位加法器的进位输入信号cin相接。
三、实验内容:
1.QuartusII软件的熟悉
熟悉QuartusⅡ环境下原理图的设计方法和流程,可参考课本第4章的内容,重点掌握层次化的设计方法。
2.设计1位全加器原理图
设计的原理图如下所示:
VHDL源程序如下(行为描述):
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityf_add_bevis
port
(
A:
instd_logic;
B:
instd_logic;
CIN:
instd_logic;
S:
outstd_logic;
CO:
outstd_logic
);
endentity;
architecturebevoff_add_bevis
begin
(CO,S)<=('0',A)+('0',B)+('0',CIN);
endbev;
VHDL源程序如下(行为描述)的RTL与technologymap视图
VHDL源程序如下(数据流描述):
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entityf_add_flis
port
(
A:
instd_logic;
B:
instd_logic;
CIN:
instd_logic;
S:
OUTstd_logic;
CO:
outstd_logic
);
endentity;
architecturefloff_add_flis
begin
S<=AXORBXORCIN;
CO<=((AXORB)ANDCIN)OR(AANDB);
endfl;
VHDL源程序如下(数据流描述)的RTL与technologymap视图:
VHDL源程序如下(结构化描述):
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entityf_add_conis
port
(
A:
instd_logic;
B:
instd_logic;
CIN:
instd_logic;
S:
OUTstd_logic;
CO:
outstd_logic
);
endentity;
architectureconoff_add_conis
COMPONENThadd_vhd
PORT
(
a:
INSTD_LOGIC;
b:
INSTD_LOGIC;
co:
OUTSTD_LOGIC;
s:
OUTSTD_LOGIC
);
ENDCOMPONENT;
SIGNALS1:
STD_LOGIC;
SIGNALCO1:
STD_LOGIC;
SIGNALCO2:
STD_LOGIC;
begin
h_add1:
hadd_vhd
portmap
(
a=>a,
B=>B,
S=>S1,
CO=>CO1
);
h_add2:
hadd_vhd
portmap
(
a=>S1,
B=>CIN,
S=>S,
CO=>CO2
);
CO<=CO1ORCO2;
endcon;
VHDL源程序如下(结构化描述)的RTL与technologymap视图:
Testbench文件源程序如下:
LIBRARYcycloneiii;
LIBRARYieee;
USEcycloneiii.cycloneiii_components.all;
USEieee.std_logic_1164.all;
ENTITYf_add_fl_tbIS
END;
ARCHITECTUREf_add_fl_tb_archOFf_add_fl_tbIS
SIGNALA:
STD_LOGIC:
='0';
SIGNALCO:
STD_LOGIC;
SIGNALCIN:
STD_LOGIC:
='0';
SIGNALB:
STD_LOGIC:
='0';
SIGNALS:
STD_LOGIC;
COMPONENTf_add_fl
PORT(
A:
inSTD_LOGIC;
CO:
bufferSTD_LOGIC;
CIN:
inSTD_LOGIC;
B:
inSTD_LOGIC;
S:
bufferSTD_LOGIC);
ENDCOMPONENT;
BEGIN
DUT:
f_add_fl
PORTMAP(
A=>A,
CO=>CO,
CIN=>CIN,
B=>B,
S=>S);
A<=NOTAAFTER0.25US;
B<=NOTBAFTER0.5US;
CIN<=NOTCINAFTER1US;
END;
功能仿真波形如下:
时序仿真波形如下:
3.利用层次化原理图方法设计4位全加器
(1)生成新的空白原理图,作为4位全加器设计输入
(2)利用已经生成的1位全加器作为电路单元,设计4位全加器。
原理图设计如下(结构化描述):
原理图设计如下(结构化描述)的RTL与technologymap视图:
VHDL源程序如下(结构化描述):
libraryieee;
useieee.std_logic_1164.all;
useieee.numeric_std.all;
entityfadd4_conis
port
(
A0:
INSTD_LOGIC;
A1:
INSTD_LOGIC;
A2:
INSTD_LOGIC;
A3:
INSTD_LOGIC;
B0:
INSTD_LOGIC;
B1:
INSTD_LOGIC;
B2:
INSTD_LOGIC;
B3:
INSTD_LOGIC;
S0:
OUTSTD_LOGIC;
S1:
OUTSTD_LOGIC;
S2:
OUTSTD_LOGIC;
S3:
OUTSTD_LOGIC;
CO:
OUTSTD_LOGIC
);
endentity;
architectureconoffadd4_conis
COMPONENTfadd1_vhd
PORT
(
A:
INSTD_LOGIC;
B:
INSTD_LOGIC;
CIN:
INSTD_LOGIC;
S:
OUTSTD_LOGIC;
CO:
OUTSTD_LOGIC
);
ENDCOMPONENT;
SIGNALCO0:
STD_LOGIC;
SIGNALCO1:
STD_LOGIC;
SIGNALCO2:
STD_LOGIC;
SIGNALCO3:
STD_LOGIC;
begin
f_add1:
fadd1_vhd
portmap
(
A=>A0,
B=>B0,
CIN=>'0',
S=>S0,
CO=>CO0
);
f_add2:
fadd1_vhd
portmap
(
A=>A1,
B=>B1,
CIN=>CO0,
S=>S1,
CO=>CO1
);
f_add3:
fadd1_vhd
portmap
(
A=>A2,
B=>B2,
CIN=>CO1,
S=>S2,
CO=>CO2
);
f_add4:
fadd1_vhd
portmap
(
A=>A3,
B=>B3,
CIN=>CO2,
S=>S3,
CO=>CO3
);
CO<=CO3;
endcon;
VHDL源程序如下(结构化描述)的RTL与technologymap视图:
Testbench源程序如下:
LIBRARYcycloneiii;
LIBRARYieee;
USEcycloneiii.cycloneiii_components.all;
USEieee.std_logic_1164.all;
ENTITYfadd4_con_tbIS
END;
ARCHITECTUREfadd4_con_tb_archOFfadd4_con_tbIS
SIGNALB0:
STD_LOGIC:
='0';
SIGNALB1:
STD_LOGIC:
='0';
SIGNALB2:
STD_LOGIC:
='0';
SIGNALB3:
STD_LOGIC:
='0';
SIGNALA0:
STD_LOGIC:
='0';
SIGNALCO:
STD_LOGIC;
SIGNALA1:
STD_LOGIC:
='0';
SIGNALA2:
STD_LOGIC:
='0';
SIGNALS0:
STD_LOGIC;
SIGNALA3:
STD_LOGIC:
='0';
SIGNALS1:
STD_LOGIC;
SIGNALS2:
STD_LOGIC;
SIGNALS3:
STD_LOGIC;
COMPONENTfadd4_con
PORT(
B0:
inSTD_LOGIC;
B1:
inSTD_LOGIC;
B2:
inSTD_LOGIC;
B3:
inSTD_LOGIC;
A0:
inSTD_LOGIC;
CO:
bufferSTD_LOGIC;
A1:
inSTD_LOGIC;
A2:
inSTD_LOGIC;
S0:
bufferSTD_LOGIC;
A3:
inSTD_LOGIC;
S1:
bufferSTD_LOGIC;
S2:
bufferSTD_LOGIC;
S3:
bufferSTD_LOGIC);
ENDCOMPONENT;
BEGIN
DUT:
fadd4_con
PORTMAP(
B0=>B0,
B1=>B1,
B2=>B2,
B3=>B3,
A0=>A0,
CO=>CO,
A1=>A1,
A2=>A2,
S0=>S0,
A3=>A3,
S1=>S1,
S2=>S2,
S3=>S3);
A0<=notA0after0.1us;
A1<=notA1after0.2us;
A2<=notA2after0.4us;
A3<=notA3after0.8us;
B0<=notB0after0.2us;
B1<=notB1after0.4us;
B2<=notB2after0.8us;
B3<=notB3after1.6us;
END;
最终的功能仿真波形如下:
最终的时序仿真波形如下:
四、思考题
1、试着论述功能仿真和时序仿真的差别?
2、试着论述结构体的行为描述、数据流描述和结构描述的区别?
3、如何构建四位并行加法器?