VHDL一些常用程序EDA必考.docx
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VHDL一些常用程序EDA必考
常用程序:
●1/4位加法器、1/4位减法器、2/4/8位数据选择器、D/8D锁存器、D触发器、4位移位寄存器、2-4/3-8译码器、用with-select或者when-else设计同或门、异或门和或非门等、根据逻辑表达式编程等等,如F=ABC+(D+E)+GH。
加减法器件的设计要考虑如何采用元件例化语句和生成语句设计。
六、十进制计数器的设计
●布置的第3章课后作业
看了几本作业,大概清楚了哪些程序有难度,下面仅列出部分程序供大家参考:
【减法器】
1位减法器:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.all;
entitysubber1is
port(a,b,cin:
instd_logic;
s:
outstd_logic;
cout:
outstd_logic);
endsubber1;
architectureoneofsubber1is
begin
s<=(axorb)xorcin;
cout<=((nota)nandb)nand(not(axorb)nandcin);
endone;
4位减法器:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEWORK.my_pkg.all;
entitysubber4is
port(a,b:
instd_logic_vector(3downto0);
cin:
instd_logic;
s:
outstd_logic_vector(3downto0);
cout:
outstd_logic);
endsubber4;
architectureoneofsubber4is
signalcout0,cout1,cout2:
std_logic;
begin
u1:
subber1portmap(a(0),b(0),cin,s(0),cout0);
u2:
subber1portmap(a
(1),b
(1),cout0,s
(1),cout1);
u3:
subber1portmap(a
(2),b
(2),cout1,s
(2),cout2);
u4:
subber1portmap(a(3),b(3),cout2,s(3),cout);
endone;
程序包:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
PACKAGEmy_pkgIS
Componentsubber1
port(a,b:
instd_logic;
cin:
instd_logic;
s:
outstd_logic;
cout:
outstd_logic);
ENDComponent;
Componentsubber4
port(a,b:
instd_logic_vector(3downto0);
cin:
instd_logic;
s:
outstd_logic_vector(3downto0);
cout:
outstd_logic);
ENDComponent;
endmy_pkg;
16位减法器:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEWORK.my_pkg.all;
entitysubber16is
port(a,b:
instd_logic_vector(15downto0);
cin:
instd_logic;
s:
outstd_logic_vector(15downto0);
cout:
outstd_logic);
endsubber16;
architectureoneofsubber16is
signalcout0,cout1,cout2:
std_logic;
begin
u1:
subber4portmap(a(3downto0),b(3downto0),cin,s(3downto0),cout0);
u2:
subber4portmap(a(7downto4),b(7downto4),cout0,s(7downto4),cout1);
u3:
subber4portmap(a(11downto8),b(11downto8),cout1,s(11downto8),cout2);
u4:
subber4portmap(a(15downto12),b(15downto12),cout2,s(15downto12),cout);
endone;
【D触发器】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYdchufaqiIS
PORT(clk,d,clr:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDdchufaqi;
ARCHITECTUREexample2OFdchufaqiIS
BEGIN
process(clk,d,clr)
begin
if(clr='0')thenq<='0';
elsif(clk'eventandclk='1')then
q<=d;
endif;
endprocess;
ENDexample2;
【4位移位寄存器】
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYshifterIS
PORT(din,clk:
INbit;
dout:
outbit);
ENDshifter;
ARCHITECTUREaOFshifterIS
componentdff
port(d,clk:
inbit;
q:
outbit);
endcomponentdff;
signald:
bit_vector(0to4);
BEGIN
d(0)<=din;
u1:
dffportmap(d(0),clk,d
(1));
u2:
dffportmap(d
(1),clk,d
(2));
u3:
dffportmap(d=>d
(2),clk=>clk,q=>d(3));
u4:
dffportmap(d=>d(3),clk=>clk,q=>d(4));
dout<=d(4);
ENDa;
【8D锁存器】
(1)LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYlatch1IS--1位锁存器的设计
PORT(d:
INSTD_LOGIC;
ena:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDlatch1;
ARCHITECTUREexample4OFlatch1IS
SIGNALsig_save:
STD_LOGIC:
=‘0’;
BEGIN
PROCESS(d,ena)
BEGIN
IFena='1'THEN
Sig_save<=D;
ENDIF;
Q<=sig_save;
ENDPROCESS;
ENDexample4;
(2)LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
PACKAGEmy_pkgIS
COMPONENTlatch1--latch1入程序包
PORT(d:
INSTD_LOGIC;
ena:
INSTD_LOGIC;
q:
OUTSTD_LOGIC);
ENDCOMPONENT;
ENDmy_pkg;
(3)LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEWORK.my_pkg.ALL;
ENTITYct74373IS--8D锁存器的设计
PORT(d:
INSTD_LOGIC_VECTOR(7DOWNTO0);
oen,g:
INSTD_LOGIC;
q:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDct74373;
ARCHITECTUREoneOFct74373IS
SIGNALsigsave:
STD_LOGIC_VECTOR(7DOWNTO0);
BEGIN
Gelatch:
fornin0to7GENERATE
Latchx:
latch1portmap(d(n),g,sigsave(n));
ENDGENERATE;
Q<=sigsavewhenoen=‘0’else
“ZZZZZZZZ”;
ENDone;
【根据逻辑表达式编程等等,如F=ABC+(D+E)+GH】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
entitycytestis
port(a,b,c,d,e,g,h:
instd_logic;
f:
outstd_logic);
endcytest;
architectureoneofcytestis
signalt1,t2,t3:
std_logic;
begin
t1<=aandbandc;
t2<=dore;
t3<=gandh;
f<=t1ort2ort3;
endone;
【六进制计数器】
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT6IS
PORT(CLK,CLRN,ENA,LDN:
INSTD_LOGIC;
D:
INSTD_LOGIC_VECTOR(3DOWNTO0);
Q:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);
COUT:
OUTSTD_LOGIC);
ENDCNT6;
ARCHITECTUREONEOFCNT6IS
SIGNALCI:
STD_LOGIC_VECTOR(3DOWNTO0):
="0000";
BEGIN
PROCESS(CLK,CLRN,ENA,LDN,CI)
BEGIN
IFCLRN='0'THENCI<="0000";
ELSIFCLK'EVENTANDCLK='1'THEN
IFLDN='0'THENCI<=D;
ELSIFENA='1'THEN
IFCI<5THENCI<=CI+1;
ELSECI<="0000";
ENDIF;
ENDIF;
ENDIF;
Q<=CI;
ENDPROCESS;
COUT<=CI(0)ANDCI
(2);
ENDONE;
【第3章课后作业——3.16】,用VHDL设计4选1数据选择器,然后用生成语句设计双4选1数据选择器
(1)LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYmux4_1IS
PORT(a,b,c,d:
INSTD_LOGIC;
s:
INSTD_LOGIC_vector(1downto0);
z:
OUTSTD_LOGIC);
ENDmux4_1;
ARCHITECTUREexample3OFmux4_1IS
BEGIN
PROCESS(a,b,c,d,s)
BEGIN
CASEsIS
WHEN"00"=>z<=a;
WHEN"01"=>z<=b;
WHEN"10"=>z<=c;
WHEN"11"=>z<=d;
WHENOTHERS=>z<='X';
ENDCASE;
ENDPROCESS;
ENDexample3;
(2)LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
PACKAGEmypkgIS
COMPONENTmux4_1
PORT(a,b,c,d:
INSTD_LOGIC;
s:
INSTD_LOGIC_vector(1downto0);
z:
OUTSTD_LOGIC);
ENDCOMPONENT;
ENDmypkg;
(3)LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEWORK.mypkg.ALL;
ENTITYdoublemux41IS
PORT(aa,bb,cc,dd:
INSTD_LOGIC_VECTOR(1DOWNTO0);
sel:
INSTD_LOGIC_VECTOR(1DOWNTO0);
q:
OUTSTD_LOGIC_VECTOR(1DOWNTO0));
ENDdoublemux41;
ARCHITECTUREoneOFdoublemux41IS
BEGIN
gemux41:
fornin0to1generate
ux:
mux4_1portmap(aa(n),bb(n),cc(n),dd(n),sel,q(n));
endgenerate;
endone;
【4-16译码器】
updowncnt8
libraryieee;
useieee.std_logic_1164.all;
entityupdowncnt8is
port(clr,clk,ena,load,updown:
instd_logic;
d:
inintegerrange0to255;
cout:
outstd_logic;
q:
bufferintegerrange0to255);
endupdowncnt8;
architectureoneofupdowncnt8is
begin
process(clk,ena,clr,d,load,updown)
begin
ifclr='0'then
q<=0;
elsifclk'eventandclk='1'then
ifload='1'then
q<=d;
elsifena='1'then
ifupdown='0'thenq<=q-1;
ifq=0thencout<='0';endif;
elseq<=q+1;
ifq=255thencout<='1';
elsecout<='0';endif;
endif;
endif;
endif;
endprocess;
endone;
还有一些题的参考程序大家都可以在书上或者是课件中找到,请大家务必认真仔细,做题时最重要一点,就是要看清题意!
比如加减计数器的设计,看清楚什么时候加法计数,什么时候减法计数。
另外,所有语句的格式务必看清楚,如when-else和with-select语句格式中,目标信号只出现一次等等。
BCD码加法器:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityBCD_ADDis
port(bcd_a:
instd_logic_vector(3downto0);
bcd_b:
instd_logic_vector(3downto0);
bcd_c:
outstd_logic_vector(4downto0));
endBCD_ADD;
architecturebehaveofBCD_ADDis
signalbin_c:
std_logic_vector(4downto0);
begin
bin_c<=('0'&bcd_a)+bcd_b;
bcd_c<=bin_cwhenbin_c<=9
else
bin_c+6;
endbehave;
法二:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitybcdis
port(a,b:
instd_logic_vector(3downto0);
y:
outstd_logic_vector(4downto0));
endbcd;
architecturebhofbcdis
signalf:
std_logic_vector(4downto0);
signalm:
std_logic_vector(4downto0);
signaln:
std_logic_vector(4downto0);
begin
m<='0'&a;
n<='0'&b;
f<=m+n;
y<=fwhenf<"01010"else
f+"00110"when"01001""00000";
endbh;
endprocess;
endart;;
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
useieee.std_logic_arith.all;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYadd4IS
PORT(C4:
INSTD_LOGIC;--前一位的进位C
A4:
INSTD_LOGIC_VECTOR(3DOWNTO0);--被加数A
B4:
INSTD_LOGIC_VECTOR(3DOWNTO0);--被加数B
S4:
OUTSTD_LOGIC_VECTOR(3DOWNTO0);--相加的和S
CO4:
OUTSTD_LOGIC);--相加产生的进位C
ENDENTITYadd4;
ARCHITECTUREARTOFadd4IS
SIGNALS5:
STD_LOGIC_VECTOR(4DOWNTO0);
SIGNALA5,B5:
STD_LOGIC_VECTOR(4DOWNTO0);
BEGIN
A5<='0'&A4;--扩展被加数A高位为0
B5<='0'&B4;--扩展被加数B高位为0
S5<=A5+B5+C4;--二数相加,并加上前一位的进位
S4<=S5(3DOWNTO0);--相加和的结果
CO4<=S5(4);--相加后的进位
ENDARCHITECTUREART;
----------------------------------
如下举例说明
----------------------------------
设A=0110,B=1011,CIN=0,
则00110
+01011
+0
-------------------------
10001
S=0001,COUT=1;
(注:
把A、B扩展成5位是为了保留相加后的进位)
----------------------------------