VHDL一些常用程序EDA必考.docx

1、VHDL一些常用程序EDA必考常用程序：1/4位加法器、1/4位减法器、2/4/8位数据选择器、D/8D锁存器、D触发器、4位移位寄存器、2-4/3-8译码器、用with-select或者when-else设计同或门、异或门和或非门等、根据逻辑表达式编程等等，如F= ABC+(D+E)+GH。加减法器件的设计要考虑如何采用元件例化语句和生成语句设计。六、十进制计数器的设计布置的第3章课后作业看了几本作业，大概清楚了哪些程序有难度，下面仅列出部分程序供大家参考：【减法器】1位减法器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE.STD_LOG

2、IC_UNSIGNED.all;entity subber1 isport(a,b,cin:in std_logic; s:out std_logic; cout: out std_logic); end subber1;architecture one of subber1 isbegins= (a xor b) xor cin;cout= (not a)nand b)nand(not(a xor b) nand cin);end one;4位减法器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE WORK.my_pkg.all;entity sub

3、ber4 isport(a,b:in std_logic_vector(3 downto 0); cin: in std_logic; s:out std_logic_vector(3 downto 0); cout: out std_logic); end subber4;architecture one of subber4 issignal cout0,cout1,cout2: std_logic;beginu1: subber1 port map(a(0),b(0),cin,s(0),cout0);u2: subber1 port map(a(1),b(1),cout0,s(1),co

4、ut1);u3: subber1 port map(a(2),b(2),cout1,s(2),cout2);u4: subber1 port map(a(3),b(3),cout2,s(3),cout);end one;程序包：LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL;PACKAGE my_pkg ISComponent subber1port(a,b:in std_logic; cin: in std_logic; s:out std_logic; cout: out std_logic); END Component;Component subbe

5、r4port(a,b:in std_logic_vector(3 downto 0); cin: in std_logic; s:out std_logic_vector(3 downto 0); cout: out std_logic); END Component;end my_pkg;16位减法器：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE WORK.my_pkg.all;entity subber16 isport( a,b:in std_logic_vector(15 downto 0); cin: in std_logic; s:out

6、 std_logic_vector(15 downto 0); cout: out std_logic); end subber16;architecture one of subber16 issignal cout0,cout1,cout2: std_logic;beginu1: subber4 port map(a(3 downto 0),b(3 downto 0),cin,s(3 downto 0),cout0);u2: subber4 port map(a(7 downto 4),b(7 downto 4),cout0,s(7 downto 4),cout1);u3: subber4

7、 port map(a(11 downto 8),b(11 downto 8),cout1,s(11 downto 8),cout2);u4: subber4 port map(a(15 downto 12),b(15 downto 12),cout2,s(15 downto 12),cout);end one;【D触发器】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY dchufaqi ISPORT(clk,d,clr:IN STD_LOGIC; q:OUT STD_LOGIC);END dchufaqi;ARCHITECTURE examp

8、le2 OF dchufaqi ISBEGIN process( clk,d,clr) begin if (clr=0) then q=0; elsif (clkevent and clk=1) then q=d; end if; end process;END example2;【4位移位寄存器】LIBRARY ieee;USE ieee.std_logic_1164.all;ENTITY shifter IS PORT(din,clk: IN bit; dout : out bit);END shifter;ARCHITECTURE a OF shifter IS component df

9、f port(d,clk: in bit; q: out bit); end component dff;signal d: bit_vector(0 to 4);BEGIN d(0)d(2),clk=clk,q=d(3); u4:dff port map(d=d(3),clk=clk,q=d(4); dout=d(4);END a;【8D锁存器】（1）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; ENTITY latch1 IS -1位锁存器的设计PORT ( d :IN STD_LOGIC; ena :IN STD_LOGIC; q :OUT STD_

10、LOGIC);END latch1;ARCHITECTURE example4 OF latch1 ISSIGNAL sig_save:STD_LOGIC:=0;BEGIN PROCESS (d,ena) BEGIN IF ena=1 THEN Sig_save=D; END IF; Q=sig_save; END PROCESS;END example4;（2）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; PACKAGE my_pkg ISCOMPONENT latch1 -latch1入程序包PORT ( d :IN STD_LOGIC; ena :I

11、N STD_LOGIC; q :OUT STD_LOGIC);END COMPONENT;END my_pkg;（3）LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; USE WORK.my_pkg.ALL;ENTITY ct74373 IS -8D锁存器的设计PORT (d: IN STD_LOGIC_VECTOR(7 DOWNTO 0); oen, g: IN STD_LOGIC; q: OUT STD_LOGIC _VECTOR(7 DOWNTO 0);END ct74373;ARCHITECTURE one OF ct74373 ISSIGNAL si

12、gsave: STD_LOGIC_VECTOR(7 DOWNTO 0);BEGIN Gelatch: for n in 0 to 7 GENERATELatchx: latch1 port map(d(n),g,sigsave(n); END GENERATE;Q=sigsave when oen=0 else “ZZZZZZZZ”;END one;【根据逻辑表达式编程等等，如F= ABC+(D+E)+GH】LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; entity cytest isport(a,b,c,d,e,g,h: in std_logic; f

13、: out std_logic); end cytest;architecture one of cytest issignal t1, t2,t3: std_logic; begin t1= a and b and c; t2= d or e; t3= g and h; f= t1 or t2 or t3; end one;【六进制计数器】LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE IEEE. STD_LOGIC_UNSIGNED.ALL;ENTITY CNT6 IS PORT (CLK, CLRN, ENA, LDN: IN STD_LOGIC

14、; D: IN STD_LOGIC_VECTOR(3 DOWNTO 0); Q: OUT STD_LOGIC_VECTOR(3 DOWNTO 0); COUT: OUT STD_LOGIC);END CNT6;ARCHITECTURE ONE OF CNT6 IS SIGNAL CI: STD_LOGIC_VECTOR(3 DOWNTO 0):=0000;BEGIN PROCESS(CLK, CLRN, ENA, LDN,CI) BEGIN IF CLRN=0 THEN CI=0000; ELSIF CLKEVENT AND CLK=1 THEN IF LDN=0 THEN CI=D; ELS

15、IF ENA=1 THEN IF CI5 THEN CI=CI+1; ELSE CI=0000; END IF; END IF; END IF; Q=CI; END PROCESS; COUT z z z z z = X; END CASE; END PROCESS;END example3;（2） LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL; PACKAGE mypkg ISCOMPONENT mux4_1 PORT(a,b,c,d:IN STD_LOGIC; s:IN STD_LOGIC_vector(1 downto 0); z:OUT STD_LO

16、GIC);END COMPONENT;END mypkg;（3） LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;USE WORK.mypkg.ALL;ENTITY doublemux41 ISPORT(aa,bb,cc,dd:IN STD_LOGIC_VECTOR(1 DOWNTO 0); sel:IN STD_LOGIC_VECTOR(1 DOWNTO 0); q:OUT STD_LOGIC_VECTOR(1 DOWNTO 0);END doublemux41;ARCHITECTURE one OF doublemux41 ISBEGIN gemux41:

17、 for n in 0 to 1 generateux: mux4_1 port map(aa(n),bb(n),cc(n),dd(n),sel,q(n);end generate;end one;【4-16译码器】updowncnt8library ieee;use ieee.std_logic_1164.all;entity updowncnt8 is port(clr,clk,ena,load,updown:in std_logic; d: in integer range 0 to 255; cout:out std_logic; q:buffer integer range 0 to

18、 255); end updowncnt8; architecture one of updowncnt8 is begin process (clk,ena,clr,d,load,updown) begin if clr=0 then q= 0; elsif clkevent and clk=1 then if load =1 then q=d; elsif ena=1 then if updown=0then q=q-1; if q = 0 then cout =0; end if; else q= q+1; if q =255 then cout =1; else cout =0; en

19、d if ; end if; end if; end if; end process; end one;还有一些题的参考程序大家都可以在书上或者是课件中找到，请大家务必认真仔细，做题时最重要一点，就是要看清题意！比如加减计数器的设计，看清楚什么时候加法计数，什么时候减法计数。另外，所有语句的格式务必看清楚，如when-else和with-select语句格式中，目标信号只出现一次等等。BCD码加法器:library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;entity BCD_ADD isport( bc

20、d_a: in std_logic_vector(3 downto 0); bcd_b: in std_logic_vector(3 downto 0); bcd_c:out std_logic_vector(4 downto 0);end BCD_ADD;architecture behave of BCD_ADD issignal bin_c: std_logic_vector(4 downto 0);begin bin_c=(0&bcd_a)+bcd_b; bcd_c=bin_c when bin_c=9 else bin_c+6; end behave;法二：library ieee;

21、use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity bcd isport (a,b:in std_logic_vector(3 downto 0); y:out std_logic_vector(4 downto 0);end bcd;architecture bh of bcd issignal f:std_logic_vector(4 downto 0);signal m:std_logic_vector(4 downto 0);signal n:st

22、d_logic_vector(4 downto 0);beginm=0&a;n=0&b;f=m+n;y=f when f01010 else f+00110 when 01001f and f10011 else 00000;end bh;end process; end art;LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;use ieee.std_logic_arith.all;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY add4 ISPORT(C4: IN STD_LOGIC;-前一位的进位C A4: IN STD_L

23、OGIC_VECTOR(3 DOWNTO 0);-被加数A B4: IN STD_LOGIC_VECTOR(3 DOWNTO 0);-被加数B S4: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);-相加的和S CO4: OUT STD_LOGIC);-相加产生的进位CEND ENTITY add4;ARCHITECTURE ART OF add4 ISSIGNAL S5: STD_LOGIC_VECTOR(4 DOWNTO 0);SIGNAL A5,B5: STD_LOGIC_VECTOR(4 DOWNTO 0);BEGIN A5=0&A4;-扩展被加数A高位为0B5=0&B4;-扩展被加数B高位为0S5=A5+B5+C4;-二数相加,并加上前一位的进位S4=S5(3 DOWNTO 0);-相加和的结果CO4=S5(4);-相加后的进位END ARCHITECTURE ART;- 如下举例说明-设A=0110，B=1011，CIN=0，则 0 0110 + 0 1011 + 0- 1 0001S=0001,COUT=1;(注：把A、B扩展成5位是为了保留相加后的进位)-