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毕业设计方案英文文献单片机中英文文献翻译
AT89C51的简况
TheGeneralSituationofAT89C51
Chapter1TheapplicationofAT89C51
Microcontrollersareusedinamultitudeofcommercialapplicationssuchasmodems,motor-controlsystems,airconditionercontrolsystems,automotiveengineandamongothers.Thehighprocessingspeedandenhancedperipheralsetofthesemicrocontrollersmakethemsuitableforsuchhigh-speedevent-basedapplications.However,thesecriticalapplicationdomainsalsorequirethatthesemicrocontrollersarehighlyreliable.Thehighreliabilityandlowmarketriskscanbeensuredbyarobusttestingprocessandapropertoolsenvironmentforthevalidationofthesemicrocontrollersbothatthecomponentandatthesystemlevel.IntelPlaformEngineeringdepartmentdevelopedanobject-orientedmulti-threadedtestenvironmentforthevalidationofitsAT89C51automotivemicrocontrollers.ThegoalsofthisenvironmentwasnotonlytoprovidearobusttestingenvironmentfortheAT89C51automotivemicrocontrollers,buttodevelopanenvironmentwhichcanbeeasilyextendedandreusedforthevalidationofseveralotherfuturemicrocontrollers.TheenvironmentwasdevelopedinconjunctionwithMicrosoftFoundationClasses(AT89C51>.Thepaperdescribesthedesignandmechanismofthistestenvironment,itsinteractionswithvarioushardware/softwareenvironmentalcomponents,andhowtouseAT89C51.
1.1Introduction
The8-bitAT89C51CHMOSmicrocontrollersaredesignedtohandlehigh-speedcalculationsandfastinput/outputoperations.MCS51microcontrollersaretypicallyusedforhigh-speedeventcontrolsystems.Commercialapplicationsincludemodems,motor-controlsystems,printers,photocopiers,airconditionercontrolsystems,diskdrives,andmedicalinstruments.TheautomotiveindustryuseMCS51microcontrollersinengine-controlsystems,airbags,suspensionsystems,andantilockbrakingsystems(ABS>.TheAT89C51isespeciallywellsuitedtoapplicationsthatbenefitfromitsprocessingspeedandenhancedon-chipperipheralfunctionsset,suchasautomotivepower-traincontrol,vehicledynamicsuspension,antilockbraking,andstabilitycontrolapplications.Becauseofthesecriticalapplications,themarketrequiresareliablecost-effectivecontrollerwithalowinterruptlatencyresponse,abilitytoservicethehighnumberoftimeandeventdrivenintegratedperipheralsneededinrealtimeapplications,andaCPUwithaboveaverageprocessingpowerinasinglepackage.Thefinancialandlegalriskofhavingdevicesthatoperateunpredictablyisveryhigh.Onceinthemarket,particularlyinmissioncriticalapplicationssuchasanautopilotoranti-lockbrakingsystem,mistakesarefinanciallyprohibitive.Redesigncostscanrunashighasa$500K,muchmoreifthefixmeans2backannotatingitacrossaproductfamilythatsharethesamecoreand/orperipheraldesignflaw.Inaddition,fieldreplacementsofcomponentsisextremelyexpensive,asthedevicesaretypicallysealedinmoduleswithatotalvalueseveraltimesthatofthecomponent.Tomitigatetheseproblems,itisessentialthatcomprehensivetestingofthecontrollersbecarriedoutatboththecomponentlevelandsystemlevelunderworstcaseenvironmentalandvoltageconditions.Thiscompleteandthoroughvalidationnecessitatesnotonlyawell-definedprocessbutalsoaproperenvironmentandtoolstofacilitateandexecutethemissionsuccessfully.IntelChandlerPlatformEngineeringgroupprovidespostsiliconsystemvalidation(SV>ofvariousmicro-controllersandprocessors.Thesystemvalidationprocesscanbebrokenintothreemajorparts.Thetypeofthedeviceanditsapplicationrequirementsdeterminewhichtypesoftestingareperformedonthedevice.
1.2TheAT89C51providesthefollowingstandardfeatures:
4KbytesofFlash,128bytesofRAM,32I/Olines,two16-bittimer/counters,afivevectortwo-levelinterruptarchitecture,afulldupleser-ialport,on-chiposcillatorandclockcircuitry.Inaddition,theAT89C51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialportandinterruptsys-temtocontinuefunctioning.ThePower-downModesavestheRAMcontentsbutfreezestheoscil–latordisablingallotherchipfunctionsuntilthenexthardwarereset.
Figure1-2-1BlockDiagram
1-3PinDescription
VCCSupplyvoltage.
GNDGround.
Port0:
Port0isan8-bitopen-drainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashighimpedanceinputs.Port0mayalsobeconfiguredtobethemultiplexedloworderaddress/databusduringaccessestoexternalprogramanddatamemory.InthismodeP0hasinternalpullups.Port0alsoreceivesthecodebytesduringFlashprogramming,andoutputsthecodebytesduringprogramverification.Externalpullupsarerequiredduringprogramverification.
Port1:
Port1isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort1outputbufferscansink/so-urcefourTTLinputs.When1sarewrittentoPort1pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL>becauseoftheinternalpullups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.
Port2:
Port2isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL>becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoPort2pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL>becauseoftheinternalpullups.Port2emitsthehigh-orderaddressbyteduringfetchesfromexternalprogrammemoryandduringaccessestoexternaldatamemorythatuse16-bitaddresses(MOVX@DPTR>.Inthisapplication,itusesstronginternalpull-upswhenemitting1s.Duringaccessestoexternaldatamemorythatuse8-bitaddresses(MOVX@RI>,Port2emitsthecontentsoftheP2SpecialFunctionRegister.Port2alsoreceivesthehigh-orderaddressbitsandsomecontrolsignalsdurinFlashprogrammingandverification.
Port3:
Port3isan8-bitbi-directionalI/Oportwithinternalpullups.ThePort3outputbufferscansink/sou-rcefourTTLinputs.When1sarewrittentoPort3pinstheyarepulledhighbytheinternalpullupsandcanbeusedasinputs.Asinputs,Port3pinsthatareexternallybeingpulledlowwillsourcecurrent(IIL>becauseofthepullups.
Port3alsoservesthefunctionsofvariousspecialfeaturesoftheAT89C51aslistedbelow:
RST:
Resetinput.Ahighonthispinfortwomachinecycleswhiletheoscillatorisrunningresetsthedevice.
ALE/PROG:
AddressLatchEnableoutputpulseforlatchingthelowbyteoftheaddressduringaccessestoexternalmemory.Thispinisalsotheprogrampulseinput(PROG>duringFlashprogramming.InnormaloperationALEisemittedataconstantrateof1/6theoscillatorfrequency,andmaybeusedforexternaltimingorclockingpurposes.Note,however,thatoneALEpulseisskippedduri-ngeachaccesstoexternalDataMemory.Ifdesired,ALEoperationcanbedisabledbysettingbit0ofSFRlocation8EH.Withthebitset,ALEisactiveonlyduringaMOVXorMOVCinstruction.Otherwise,thepinisweaklypulledhigh.SettingtheALE-disablebithasnoeffectifthemicrocontrollerisinexternalexecutionmode.
PSEN:
ProgramStoreEnableisthereadstrobetoexternalprogrammemory.WhentheAT89C51isexecutingcodefromexternalprogrammemory,PSENisactivatedtwiceeachmachinecycle,exceptthattwoPSENactivationsareskippedduringeachaccesstoexternaldatamemory.
EA/VPP:
ExternalAccessEnable.EAmustbestrappedtoGNDinordertoenablethedevicetofetchcodefromexternalprogrammemorylocationsstartingat0000HuptoFFFFH.Note,however,thatiflockbit1isprogrammed,EAwillbeinternallylatchedonreset.EAshouldbestrappedtoVCCforinternalprogramexecutions.Thispinalsreceivesthe12-voltprogrammingenablevoltage(VPP>duringFlashprogramming,forpartsthatrequire12-voltVPP.
XTAL1:
Inputtotheinvertingoscillatoramplifierandinputtotheinternalclockoperatingcircuit.
XTAL2:
Outputfromtheinvertingoscillatoramplifier.OscillatorCharacteristicsXTAL1andXTAL2aretheinputandoutput,respectively,ofaninvertingamplifierwhichcanbeconfiguredforuseasanon-chiposcillator,asshowninFigure1.Eitheraquartzcrystalorceramicresonatormaybeused.Todrivethedevicefromanexternalclocksource,XTAL2shouldbeleftunconnectedwhileXTAL1isdrivenasshowninFigure2.Therearenorequirementsonthedutycycleoftheexternalclocksignal,sincetheinputtotheinternalclockingcircuitryisthroughadivide-by-twoflip-flop,butminimumandmaximumvoltagehighandlowtimespecificationsmustbeobserved.IdleModeInidlemode,theCPUputsitselftosleepwhilealltheonchipperipheralsremainactive.Themodeisinvokedbysoftware.Thecontentoftheon-chipRAMandallthespecialfunctionsregistersremainunchangedduringthismode.Theidlemodecanbeterminatedbyanyenabledinterruptorbyahardwarereset.Itshouldbenotedthatwhenidleisterminatedbyahardwarereset,thedevicenormallyresumesprogramexecution,fromwhereitleftoff,uptotwomachinecyclesbeforetheinternalresetalgorithmtakescontrol.On-chiphardwareinhibitsaccesstointernalRAMinthisevent,butaccesstotheportpinsisnotinhibited.Toelim