基于EDA的交通灯控制器课程设计报告.docx
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基于EDA的交通灯控制器课程设计报告
本科课程设计报告
课程名称:
EDA计数与FPGA应用设计
设计题目:
交通灯控制器
实验地点:
跨越机房
专业班级:
电信0901学号:
2009001249
学生姓名:
赵岩
指导教师:
张文爱
年月日
设计一:
三位十进制计数显示器
一、设计目的:
1、掌握时序电路中多进程的VHDL的描述方法。
2、掌握层次化设计方法。
3、熟悉EDA的仿真分析和硬件测试技术。
二、设计原理
三位十进制计数显示器分三部分完成,先设计十进制计数电路,再设计显示译码电路,最后设计一个顶层文件将两者连接起来。
三源程序
1、三位十进制计数器的三位分三个进程描述,含有同步清0信号RESET和计数使能控制信号CIN
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCOU3IS
PORT(CLK,RESET,CIN:
INSTD_LOGIC;
CO:
OUTSTD_LOGIC;
A,B,C:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOU3;
ARCHITECTUREARTOFCOU3IS
SIGNALAP,BP,CP:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
KK1:
PROCESS(CLK)
BEGIN
IF(CLK'EVENTANDCLK='1')THEN
IF(RESET='0')THEN
AP<="0000";
ELSIF(CIN='1')THEN
IF(AP="1001")THEN
AP<="0000";
ELSE
AP<=AP+'1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESSKK1;
KK2:
PROCESS(CLK)
BEGIN
IF(CLK'EVENTANDCLK='1')THEN
IF(RESET='0')THEN
BP<="0000";
ELSIF(CIN='1')AND(AP="1001")THEN
IFBP="1001"THEN
BP<="0000";
ELSE
BP<=BP+'1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESSKK2;
KK3:
PROCESS(CLK)
BEGIN
IF(CLK'EVENTANDCLK='1')THEN
IF(RESET='0')THEN
CP<="0000";
ELSIF(CIN='1')AND(AP="1001")AND(BP="1001")THEN
IFCP="1001"THEN
CP<="0000";
ELSE
CP<=CP+'1';
ENDIF;
ENDIF;
ENDIF;
ENDPROCESSKK3;
PROCESS(CLK)IS
BEGIN
IFCLK'EVENTANDCLK='1'THEN
IFAP="1001"ANDBP="1001"ANDCP="1001"THEN
CO<='1';
ELSE
CO<='0';
ENDIF;
ENDIF;
ENDPROCESS;
A<=AP;
B<=BP;
C<=CP;
ENDART;
2、七段显示译码电路VHDL设计文件
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYYIMA7IS
PORT(A:
INSTD_LOGIC_VECTOR(3DOWNTO0);
YIMA:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDYIMA7;
ARCHITECTUREARTOFYIMA7IS
BEGIN
PROCESS(A)IS
BEGIN
CASEAIS
WHEN"0000"=>YIMA<="1000000";
WHEN"0001"=>YIMA<="1111001";
WHEN"0010"=>YIMA<="0100100";
WHEN"0011"=>YIMA<="0110000";
WHEN"0100"=>YIMA<="0011001";
WHEN"0101"=>YIMA<="0010010";
WHEN"0110"=>YIMA<="0000010";
WHEN"0111"=>YIMA<="1111000";
WHEN"1000"=>YIMA<="0000000";
WHEN"1001"=>YIMA<="0010000";
WHENOTHERS=>YIMA<="1111111";
ENDCASE;
ENDPROCESS;
ENDART;
3、三位显示译码顶层文件
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYJISHUXIANSHIIS
PORT(CLK,RESET,EN:
INSTD_LOGIC;
SEG1,SEG2,SEG3:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDJISHUXIANSHI;
ARCHITECTUREARTOFJISHUXIANSHIIS
COMPONENTYIMA7
PORT(A:
INSTD_LOGIC_VECTOR(3DOWNTO0);
YIMA:
OUTSTD_LOGIC_VECTOR(6DOWNTO0));
ENDCOMPONENT;
COMPONENTCOU3
PORT(CLK,RESET,CIN:
INSTD_LOGIC;
CO:
OUTSTD_LOGIC;
A,B,C:
OUTSTD_LOGIC_VECTOR(3DOWNTO0));
ENDCOMPONENT;
SIGNALIN_A,IN_B,IN_C:
STD_LOGIC_VECTOR(3DOWNTO0);
BEGIN
U0:
COU3PORTMAP(CLK,RESET,EN,IN_A,IN_B,IN_C);
U1:
YIMA7PORTMAP(IN_A,SEG1);
U2:
YIMA7PORTMAP(IN_B,SEG2);
U3:
YIMA7PORTMAP(IN_C,SEG3);
ENDART;
四、仿真出图
五、下载到电路板
得到设计结果显示三位十进制计数
设计二:
交通灯控制器
一、设计要求
设计一个由一条支干道和一条主干道的汇合点形成的十字交叉路口的交通灯控制器,主要要求如下:
(1).主、支干道各设有一个绿、黄、红指示灯,两个显示数码管。
(2)主干道处于常允许状态,两支干道有车来才允许通行。
(3)当主、支干道有车时,两者交替通行,主干道每次放行45s,支干道每次放行25s,在每次由亮绿灯变成亮红灯转换过程中,要亮5s黄灯作为过渡,并进行减计时显示。
二、设计方案
1、分模块设计
1)、红、绿、黄灯控制模块,模块名JTDKZ;
2)、倒计时传输、控制模块XSKZ;
3)、倒计时45s——CNT45s;
4)、倒计时25s——CNT25s;
5)、倒计时5s——CNT05s。
6)、输入、输出。
2、模块设计思路
1)、JTDKZ——根据交通灯显示有4种状态,可以采用CASE语句设置选择4种状态。
设置3个输入:
CLK(时钟脉冲)、SB(支干道传感器)、SM(主干道传感器)。
2)、XSKZ——根据需要交通灯显示的不同数倒计时据设置4个输入使能信号:
EN45(45s倒计时使能信号)、EN25(25s倒计时使能信号)、EN05(5s倒计时使能信号);再设置5个倒计时计数数据输入信号将此时倒计时数据输出:
AIN45M、AIN45B、AIN25M、AIN25B、AIN05;2个输出信号使数码管显示正在倒计时的时间。
3)、CNT45S——根据倒计时计数的要求设置3个输入信号:
CLK(计数脉冲)、
EN45(计数使能)、SB(支干道传感器信号);2个输出DOUT45M、DOUT45B,分别用于主、支干道显示。
4)、CNT25s——根据倒计时计数的要求设置4个输入信号:
CLK(计数脉冲)、
EN45(计数使能)、SM(主干道传感器信号)、SB(支干道传感器信号);2个输出DOUT25M、DOUT25B,分别用于主、支干道显示。
5)、CNT05s——根据倒计时计数的要求设置3个输入信号:
CLK(计数脉冲)、
EN05B(计数使能)、EN05M(计数使能);1个输出DOUT05,用于主、支干道显示。
6)、输入输出模块,3个输入分别为:
CLK、SB、SM,2个输出分别为
DOUT1[7..0]、DOUT2[7..0]。
三、设计源程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYJTDKZIS
PORT(CLK,SM,SB:
INSTD_LOGIC;
MR,MY0,MG0,BR,BY0,BG0:
OUTSTD_LOGIC);
ENDENTITYJTDKZ;
ARCHITECTUREARTOFJTDKZIS
TYPESTATE_TYPEIS(A,B,C,D);
SIGNALSTATE:
STATE_TYPE;
BEGIN
CNT:
PROCESS(CLK)IS
VARIABLES:
INTEGERRANGE0TO45;
VARIABLECLR,EN:
BIT;
BEGIN
IF(CLK'EVENTANDCLK='1')THEN
IFCLR='0'THENS:
=0;
ELSIFEN='0'THENS:
=S;
ELSES:
=S+1;
ENDIF;
CASESTATEIS
WHENA=>MR<='0';MY0<='0';MG0<='1';BR<='1';BY0<='0';BG0<='0';
IF(SBANDSM)='1'THEN
IFS=45THENSTATE<=B;CLR:
='0';EN:
='0';
ELSESTATE<=A;CLR:
='1';EN:
='1';
ENDIF;
ELSIF(SBAND(NOTSM))='1'THENSTATE<=B;CLR:
='0';EN:
='0';
ELSESTATE<=A;CLR:
='1';EN:
='1';
ENDIF;
WHENB=>MR<='0';MY0<='1';MG0<='0';BR<='1';BY0<='0';BG0<='0';
IFS=5THENSTATE<=C;CLR:
='0';EN:
='0';
ELSESTATE<=B;CLR:
='1';EN:
='1';
ENDIF;
WHENC=>MR<='1';MY0<='0';MG0<='0';BR<='0';BY0<='0';BG0<='1';
IF(SMANDSB)='1'THEN
IFS=25THENSTATE<=D;CLR:
='0';EN:
='0';
ELSESTATE<=C;CLR:
='1';EN:
='1';
ENDIF;
ELSIFSB='0'THENSTATE<=D;CLR:
='0';EN:
='0';
ELSESTATE<=C;CLR:
='1';EN:
='1';
ENDIF;
WHEND=>MR<='1';MY0<='0';MG0<='0';BR<='0';BY0<='1';BG0<='0';
IFS=5THENSTATE<=A;CLR:
='0';EN:
='0';
ELSESTATE<=D;CLR:
='1';EN:
='1';
ENDIF;
ENDCASE;
ENDIF;
ENDPROCESSCNT;
ENDARCHITECTUREART;
设计仿真的截图:
XSKZ模块的实现
简单设计思路:
根据EN45、EN25、EN05M、EN05B的信号以及3个倒计时计数器的计数状态决定输出3个倒计时计数器中某个的状态输出。
原理图模块:
设计源程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCSKZIS
PORT(INA:
INSTD_LOGIC;
OUTA:
OUTSTD_LOGIC);
ENDENTITYCSKZ;
ARCHITECTUREARTOFCSKZIS
BEGIN
PROCESS(INA)IS
BEGIN
IFINA='1'THENOUTA<='1';
ELSEOUTA<='0';
ENDIF;
ENDPROCESS;
ENDARCHITECTUREART;
设计仿真的截图:
CNT45S模块的实现
简单思路:
CLK上升沿到来时,若到计时使能信号和SB信号有效,CNT45S开始计数,并将输入状态通过DOUT45M、DOUT45B分别输出到主、支干道显示。
设计的原理图模块:
设计源程序:
3
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT45SIS
PORT(SB,CLK,EN45:
INSTD_LOGIC;
DOUT45M,DOUT45B:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDCNT45S;
ARCHITECTUREARTOFCNT45SIS
SIGNALCNT6B:
STD_LOGIC_VECTOR(5DOWNTO0);
BEGIN
PROCESS(SB,CLK,EN45)IS
BEGIN
IFSB='0'THENCNT6B<=CNT6B-CNT6B-1;
ELSIF(CLK'EVENTANDCLK='1')THEN
IFEN45='1'THENCNT6B<=CNT6B+1;
ELSIFEN45='0'THENCNT6B<=CNT6B-CNT6B-1;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(CNT6B)IS
BEGIN
CASECNT6BIS
WHEN"000000"=>DOUT45M<="01000101";DOUT45B<="01010000";
WHEN"000001"=>DOUT45M<="01000100";DOUT45B<="01001001";
WHEN"000010"=>DOUT45M<="01000011";DOUT45B<="01001000";
WHEN"000011"=>DOUT45M<="01000010";DOUT45B<="01000111";
WHEN"000100"=>DOUT45M<="01000001";DOUT45B<="01000110";
WHEN"000101"=>DOUT45M<="01000000";DOUT45B<="01000101";
WHEN"000110"=>DOUT45M<="00111001";DOUT45B<="01000100";
WHEN"000111"=>DOUT45M<="00111000";DOUT45B<="01000011";
WHEN"001000"=>DOUT45M<="00110111";DOUT45B<="01000010";
WHEN"001001"=>DOUT45M<="00110110";DOUT45B<="01000001";
WHEN"001010"=>DOUT45M<="00110101";DOUT45B<="01000000";
WHEN"001011"=>DOUT45M<="00110100";DOUT45B<="01101001";
WHEN"001100"=>DOUT45M<="00110011";DOUT45B<="00111000";
WHEN"001101"=>DOUT45M<="00110010";DOUT45B<="00110111";
WHEN"001110"=>DOUT45M<="00110001";DOUT45B<="00110110";
WHEN"001111"=>DOUT45M<="00110000";DOUT45B<="00110101";
WHEN"010000"=>DOUT45M<="00101001";DOUT45B<="00110100";
WHEN"010001"=>DOUT45M<="00101000";DOUT45B<="00110011";
WHEN"010010"=>DOUT45M<="00100111";DOUT45B<="00110010";
WHEN"010011"=>DOUT45M<="00100110";DOUT45B<="00110001";
WHEN"010100"=>DOUT45M<="00100101";DOUT45B<="00110000";
WHEN"010101"=>DOUT45M<="00100100";DOUT45B<="00101001";
WHEN"010110"=>DOUT45M<="00100011";DOUT45B<="00101000";
WHEN"010111"=>DOUT45M<="00100010";DOUT45B<="00100111";
WHEN"011000"=>DOUT45M<="00100001";DOUT45B<="00100110";
WHEN"011001"=>DOUT45M<="00100000";DOUT45B<="00100101";
WHEN"011010"=>DOUT45M<="00011001";DOUT45B<="00100100";
WHEN"011011"=>DOUT45M<="00011000";DOUT45B<="00100011";
WHEN"011100"=>DOUT45M<="00010111";DOUT45B<="00100010";
WHEN"011101"=>DOUT45M<="00010110";DOUT45B<="00100001";
WHEN"011110"=>DOUT45M<="00010101";DOUT45B<="00100000";
WHEN"011111"=>DOUT45M<="00010100";DOUT45B<="00011001";
WHEN"100000"=>DOUT45M<="00010011";DOUT45B<="00011000";
WHEN"100001"=>DOUT45M<="00010010";DOUT45B<="00010111";
WHEN"100010"=>DOUT45M<="00010001";DOUT45B<="00010110";
WHEN"100011"=>DOUT45M<="00010000";DOUT45B<="00010101";
WHEN"100100"=>DOUT45M<="00001001";DOUT45B<="00010100";
WHEN"100101"=>DOUT45M<="00001000";DOUT45B<="00010011";
WHEN"100110"=>DOUT45M<="00000111";DOUT45B<="00010010";
WHEN"100111"=>DOUT45M<="00000110";DOUT45B<="00010001";
WHEN"101000"=>DOUT45M<="00000101";DOUT45B<="00010000";
WHEN"101001"=>DOUT45M<="00000100";DOUT45B<="00001001";
WHEN"101010"=>DOUT45M<="00000011";DOUT45B<="00001000";
WHEN"101011"=>DOUT45M<="00000010";DOUT45B<="00000111";
WHEN"101100"=>DOUT45M<="00000001";DOUT45B<="00000110";
WHENOTHERS=>DOUT45M<="00000000";DOUT45B<="00000000";
ENDCASE;
ENDPROCESS;
END;
设计仿真的截图:
CNT25S模块的实现
简单思路:
CLK上升沿到来时,若到计时使能信号、SM信号和SB信号有效,CNT25S开始计数,并将输入状态通过DOUT25M、DOUT25B分别输出到主、支干道显示。
设计的原理图模块:
设计源程序:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSI
GNED.ALL;
ENTITYCNT25SIS
PORT(SB,SM,CLK,EN25:
INSTD_LOGIC;
DOUT25M,DOUT25B:
OUTSTD_LOGIC_VECTOR(7DOWNTO0));
ENDENTITYCNT25S;
ARCHITECTUREARTOFCNT25SIS
SIGNALCNT5B:
STD_LOGIC_VECTOR(4DOWNTO0);
BEGIN
PROCESS(SB,SM,CLK,EN25)IS
BEGIN
IFSB='0'THENCNT5B<=CNT5B-CNT5B-1;
ELSIFSM='0'THENCNT5B<=CNT5B-CNT5B-1;
ELSIF(CLK'EVENTANDCLK='1')THEN
IFEN25='1'THENCNT5B<=CNT5B+1;
ELSIFEN25='0'THENCNT5B<=CNT5B-CNT5B-1;
ENDIF;
ENDIF;
ENDPROCESS;
PROCESS(CNT5B)IS
BEGIN
CASECNT5BIS
WHEN"00000"=>DOUNT25B<="00100101";DOUT25M<="00110000";
WHEN"00001"=>DOUNT25B<="00100100";DOUT25M<="00101001";
WHEN"00010"=>DOUNT25B<="00100011";DOUT25M<="00101000";
WHEN"00011"=>DOUNT25B<="00100010";DOUT25M<="00100111";
WHEN"00100"=>DOUNT25