复杂数字电路设计实验报告数字抢答器.docx
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复杂数字电路设计实验报告数字抢答器
复杂数字电路设计实验报告
——数字式竞赛抢答器
一.实验题目名称:
数字式竞赛抢答器
二.实验目的、任务和要求:
设计—个可容纳四组参赛的数字式抢答器,每组设一个按钮供抢答者使用。
抢答器具有
第一信号鉴别和锁存功能,使除第一抢答者外的按钮不起作用;设置一个主持人“复位”按钮,主持人复位后,开始抡答,第一信号鉴别锁存电路得到信号后,用指示灯显示抡答组别,扬声器发出2—3s的音响。
设置犯规电路,对提前抢答和超时答题(例如3min)的组别鸣笛示警,并由组别显示电路显示出犯规组别。
设置一个计分电路,每组开始预置10分,由主持人记分,答对一次加1分,答错一次减1分。
三.实验系统结构设计分析
1.模块划分思想和方法;
本试验系统分为第一信号鉴别、锁存模块、答题计时电路模块、计分电路模块和扫描显示模块四部分。
第—信号鉴别锁存模块的关键是准确判断出第一枪答者并将其锁存,在得到第一信号后,将输入端封锁,使其他组的抢答信号无效,可以用触发器或锁存器实现。
设置抢答按钮K1、K2、K3、K4,主持人复位信号reset,扬声器驱动信号out。
Reset=0时,第—信号鉴别、锁存电路、答题计时电路复位,在此状态下,若有枪答按钮按下,鸣笛示警并显示犯规组别;reset=1时,开始枪答,由第—信号鉴别锁存电路形成第一枪答信号,进行组别显示,控制扬声器发出音响,并启动答题计时电路,若计时时间到,主持人复位信号还没有按下则由扬声器发出犯规示警声。
计分电路是一个相对独立的模块,采用十进制加/减计数器、数码管数码扫描显示,设置复位信号reset1、加分信号up、减分信号down,reset1=0时,所有得分回到起始分(10分),且加分、减分信号无效;reset1=1时,由第一信号鉴别、锁存电路的输出信号选择进行加减分的组别,每按一次up,第一抢答组加—分;每按—次down,第一抢答组减一分。
硬件系统示意图如下图所示:
2.模块框图和作用;
抢答器模块框图
抢答器具有第一信号鉴别和锁存功能,使除第一抢答者外的按钮不起作用;主持人“复位”按钮,主持人复位后,开始抡答,第一信号鉴别锁存电路得到信号后,用指示灯显示抡答组别,扬声器发出2—3s的音响。
犯规电路,对提前抢答和超时答题(例如3min)的组别鸣笛示警,并由组别显示电路显示出犯规组别。
计分电路对每组开始预置10分,由主持人记分,答对一次加1分,答错一次减1分。
扫描显示模块用于实时显示各组选手的得分。
3.各模块引脚定义和作用.
时钟:
NET"clk"LOC="C9"|IOSTANDARD=lvcmos33;
加分:
NET"up"LOC="L14"|IOSTANDARD=lvttl|PULLUP;
扣分:
NET"down"LOC="L13"|IOSTANDARD=lvttl|PULLUP;
A组抢答按钮:
NET"K1"LOC="H13"|IOSTANDARD=lvttl|PULLDOWN;
B组抢答按钮:
NET"K2"LOC="V4"|IOSTANDARD=lvttl|PULLDOWN;
C组抢答按钮:
NET"K3"LOC="D18"|IOSTANDARD=lvttl|PULLDOWN;
D组抢答按钮:
NET"K4"LOC="K17"|IOSTANDARD=lvttl|PULLDOWN;
LED提示灯:
NET"outalarm"LOC="F9"|IOSTANDARD=lvttl|SLEW=slow|DRIVE=8;
抢答重置:
NET"reset"LOC="N17"|IOSTANDARD=lvttl|PULLUP;
得分重置:
NET"resetl"LOC="H18"|IOSTANDARD=lvttl|PULLUP;
LCD各使能端与数据线:
NET"LCD_RS"LOC="L18"|IOSTANDARD=LVCMOS33|DRIVE=4|SLEW=SLOW;
NET"LCD_RW"LOC="L17"|IOSTANDARD=LVCMOS33|DRIVE=4|SLEW=SLOW;
NET"LCD_EN"LOC="M18"|IOSTANDARD=LVCMOS33|DRIVE=4|SLEW=SLOW;
NET"data<3>"LOC="M15"|IOSTANDARD=LVCMOS33|DRIVE=4|SLEW=SLOW;
NET"data<2>"LOC="P17"|IOSTANDARD=LVCMOS33|DRIVE=4|SLEW=SLOW;
NET"data<1>"LOC="R16"|IOSTANDARD=LVCMOS33|DRIVE=4|SLEW=SLOW;
NET"data<0>"LOC="R15"|IOSTANDARD=LVCMOS33|DRIVE=4|SLEW=SLOW;
四.实验代码设计以及分析:
1.给出模块层次图;
2.按模块完成的代码及注释.
Justify模块(第一信号鉴别及锁存模块):
entityjustifyis
Port(K1:
inSTD_LOGIC;
K2:
inSTD_LOGIC;
K3:
inSTD_LOGIC;
K4:
inSTD_LOGIC;
reset:
inSTD_LOGIC;--不弹起的开关
clr:
inSTD_LOGIC;
output:
bufferSTD_LOGIC_VECTOR(3downto0):
="0000";
outalarm:
outSTD_LOGIC:
='0');
endjustify;
architectureBehavioralofjustifyis
signalK11,K22,K33,K44:
STD_LOGIC:
='0';
signalalarm:
STD_LOGIC:
='0';
signaltempoutput:
STD_LOGIC_VECTOR(3downto0):
="0000";
begin
alarm<=output(0)oroutput
(1)oroutput
(2)oroutput(3);--有人抢到题,该答了
K11<=K1ANDNOT(output
(1)ORoutput
(2)ORoutput(3));--禁止别人再抢答
K22<=K2ANDNOT(output(0)ORoutput
(2)ORoutput(3));
K33<=K3ANDNOT(output(0)ORoutput
(1)ORoutput(3));
K44<=K4ANDNOT(output(0)ORoutput
(1)ORoutput
(2));
FindFirst:
PROCESS(clr,reset,K11,K22,K33,K44)IS
begin
if(reset='0'orclr='0')then—清零
tempoutput(3downto0)<="0000";
elsif(K11='1')then
tempoutput(3downto0)<="0001";
elsif(K22='1')then
tempoutput(3downto0)<="0010";
elsif(K33='1')then
tempoutput(3downto0)<="0100";
elsif(K44='1')then
tempoutput(3downto0)<="1000";
endif;
endPROCESSFindFirst;
KeepValue:
PROCESS(alarm,tempoutput,reset,clr)IS—锁存
begin
if(reset='0'orclr='0')then—清零
output(3downto0)<="0000";
elsif(alarm='0')then
output(3downto0)<=tempoutput(3downto0);
endif;
endPROCESSKeepValue;
outalarm<=alarm;
endBehavioral;
Violation模块(抢答鉴别及锁存模块):
entityviolationjustifyis
Port(clk500:
inSTD_LOGIC;
K1:
inSTD_LOGIC;
K2:
inSTD_LOGIC;
K3:
inSTD_LOGIC;
K4:
inSTD_LOGIC;
clr:
inSTD_LOGIC;
reset:
inSTD_LOGIC;
output:
bufferSTD_LOGIC_VECTOR(3downto0):
="0000";
violation:
outSTD_LOGIC:
='0');
endviolationjustify;
architectureBehavioralofviolationjustifyis
signaltempoutput:
STD_LOGIC_VECTOR(3downto0):
="0000";
signalclk:
STD_LOGIC;
begin
clk<=clk500andnot(reset);
violation<=output(0)oroutput
(1)oroutput
(2)oroutput(3);--alarm+flag
FindViolation:
PROCESS(clr,clk,reset)IS
begin
if(clr='0')then—清零
tempoutput<="0000";
elsif(clk'eventandclk='1')then—有人犯规
if(K1='1')then
tempoutput(0)<='1';
endif;
if(K2='1')then
tempoutput
(1)<='1';
endif;
if(K3='1')then
tempoutput
(2)<='1';
endif;
if(K4='1')then
tempoutput(3)<='1';
endif;
endif;
endprocessFindViolation;
output<=tempoutput;
endBehavioral;
分频器:
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_ARITH.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitydivideris
Port(clk_50M:
inSTD_LOGIC;
clk_1:
outSTD_LOGIC;
clk_500:
outSTD_LOGIC);
enddivider;
architectureBehavioralofdivideris
signalCCLK_500,CCLK_1:
STD_LOGIC:
='0';
begin
process(clk_50M)
variablecount1:
integerrange1to25000000:
=1;--1hz
variablecount3:
integerrange1to50000:
=1;--500Hz
begin
if(clk_50M'EVENTandclk_50M='1')then
if(count1=25000000)then--25000000,10
count1:
=1;--1Hz
CCLK_1<=NOT(CCLK_1);
else
count1:
=count1+1;
endif;
if(count3=50000)then--50000
count3:
=1;--500Hz
CCLK_500<=NOT(CCLK_500);
else
count3:
=count3+1;
endif;
endif;
endprocess;
clk_500<=CCLK_500;--500hz
clk_1<=CCLK_1;--1hz
endBehavioral;
记分模块:
entitypointsis
Port(
input:
inSTD_LOGIC_VECTOR(3downto0);
add:
inSTD_LOGIC;
minus:
inSTD_LOGIC;
resetforpoints:
inSTD_LOGIC;
point_ten_A,point_ten_B,point_ten_C,point_ten_D:
outSTD_LOGIC_VECTOR(3downto0):
="0001";
point_one_A,point_one_B,point_one_C,point_one_D:
outSTD_LOGIC_VECTOR(3downto0):
="0000");
endpoints;
architectureBehavioralofpointsis
signalkey:
STD_LOGIC;
begin
key<=addorminus;--按下加分或减分
process(key,resetforpoints)is
variableppoint_ten_A,ppoint_ten_B,ppoint_ten_C,ppoint_ten_D:
STD_LOGIC_VECTOR(3downto0):
="0001";
variableppoint_one_A,ppoint_one_B,ppoint_one_C,ppoint_one_D:
STD_LOGIC_VECTOR(3downto0):
="0000";
begin
if(resetforpoints='0')then—分数重置
ppoint_one_A:
="0000";
ppoint_ten_A:
="0001";
ppoint_one_B:
="0000";
ppoint_ten_B:
="0001";
ppoint_one_C:
="0000";
ppoint_ten_C:
="0001";
ppoint_one_D:
="0000";
ppoint_ten_D:
="0001";
else
if(key'eventandkey='1')then—加分
if(add='1')then
if(input="0001")then
if(ppoint_one_A="1001")then
ppoint_one_A:
="0000";
ppoint_ten_A:
=ppoint_ten_A+1;
else
ppoint_one_A:
=ppoint_one_A+1;
endif;
elsif(input="0010")then
if(ppoint_one_B="1001")then
ppoint_one_B:
="0000";
ppoint_ten_B:
=ppoint_ten_B+1;
else
ppoint_one_B:
=ppoint_one_B+1;
endif;
elsif(input="0100")then
if(ppoint_one_C="1001")then
ppoint_one_C:
="0000";
ppoint_ten_C:
=ppoint_ten_C+1;
else
ppoint_one_C:
=ppoint_one_C+1;
endif;
elsif(input="1000")then
if(ppoint_one_D="1001")then
ppoint_one_D:
="0000";
ppoint_ten_D:
=ppoint_ten_D+1;
else
ppoint_one_D:
=ppoint_one_D+1;
endif;
endif;--input
elsif(minus='1')then—减分
if(input(0)='1')then
if(ppoint_one_A="0000")then
ppoint_one_A:
="1001";
ppoint_ten_A:
=ppoint_ten_A-1;
else
ppoint_one_A:
=ppoint_one_A-1;
endif;
endif;
if(input
(1)='1')then
if(ppoint_one_B="0000")then
ppoint_one_B:
="1001";
ppoint_ten_B:
=ppoint_ten_B-1;
else
ppoint_one_B:
=ppoint_one_B-1;
endif;
endif;
if(input
(2)='1')then
if(ppoint_one_C="0000")then
ppoint_one_C:
="1001";
ppoint_ten_C:
=ppoint_ten_C-1;
else
ppoint_one_C:
=ppoint_one_C-1;
endif;
endif;
if(input(3)='1')then
if(ppoint_one_D="0000")then
ppoint_one_D:
="1001";
ppoint_ten_D:
=ppoint_ten_D-1;
else
ppoint_one_D:
=ppoint_one_D-1;
endif;
endif;--input
endif;
endif;
endif;
point_one_A<=ppoint_one_A;
point_ten_A<=ppoint_ten_A;
point_one_B<=ppoint_one_B;
point_ten_B<=ppoint_ten_B;
point_one_C<=ppoint_one_C;
point_ten_C<=ppoint_ten_C;
point_one_D<=ppoint_one_D;
point_ten_D<=ppoint_ten_D;
endprocess;
endBehavioral;
防抖模块:
entityshakingis
Port(clk500:
inSTD_LOGIC;
input:
inSTD_LOGIC;
output:
outSTD_LOGIC);
endshaking;
architectureBehavioralofshakingis
signalflag:
STD_LOGIC:
='0';
begin
process(clk500,input)is
variablecount:
integer:
=0;
begin
if(clk500'eventandclk500='1')then
if(input='1'andcount=0)then—有输入,将输入延展
count:
=count+1;
flag<='1';
elsif(flag='1')then
if(count<500)then--500
count:
=count+1;
else
count:
=0;
flag<='0';
endif;
endif;
endif;
endprocess;
output<=flag;
endBehavioral;
用于判断是否答题超时的计时模块(Timer)
entitytimeris
Port(clk1:
inSTD_LOGIC;--1hz
violationflag:
inSTD_LOGIC;
input:
inSTD_LOGIC_VECTOR(3downto0);
reset:
inSTD_LOGIC;
clr:
inSTD_LOGIC;
resetforpoints:
inSTD_LOGIC;
timeout:
outSTD_LOGIC);
endtimer;
architectureBehavioraloftimeris
signalen:
STD_LOGIC;
begin
en<=resetandclrandresetforp