vhdl考试时钟.docx
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vhdl考试时钟
实
验
报
告
应用技术一班
朱晓园,汪仙仙,张明星,胡亚洲
一:
分频模块
定义clk为时钟输入引脚。
输入20MHZ的频率。
定义一个clk1hz分频和ckl100HZ分频。
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;
ENTITYFENPINIS
PORT
(
clk:
INSTD_LOGIC;
oclk:
OUTSTD_LOGIC;
oclk100hz:
OUTSTD_LOGIC
);
ENDFENPIN;
ARCHITECTUREFENPIN_architectureOFFENPINIS
BEGIN
process(clk)
variablecnt:
integerrange0to20000000;
begin
ifrising_edge(clk)then
cnt:
=cnt+1;
ifcnt<=10000000then
oclk<='1';
elseifcnt<=20000000then
cnt:
=0;
oclk<='0';
endif;
endif;
endif;
endprocess;
process(clk)
variablecnt1:
integerrange0to20000000;
begin
ifrising_edge(clk)then
ifcnt1<=200000then
cnt1:
=0;
oclk100hz<='1';
else
cnt1:
=cnt1+1;
oclk100hz<='0';
endif;
endif;
endprocess;
ENDFENPIN_architecture;
二:
按键消抖
因为机械键盘存在抖动现象,所以需要用延时,软件去抖。
这里用100HZ的频率,一旦出现低电平,就计数10次,一共100MS,然后再次检测,如果仍为低,就输出0信号。
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;
ENTITYXIAODOUIS
PORT
(
clk:
INSTD_LOGIC;
rst_key:
INSTD_LOGIC;
set_key:
INSTD_LOGIC;
position:
INSTD_LOGIC;
addup:
INSTD_LOGIC;
position_s:
INSTD_LOGIC;
addup_time:
INSTD_LOGIC;
rst_time:
OUTSTD_LOGIC;
set_time:
OUTSTD_LOGIC
);
ENDXIAODOU;
ARCHITECTUREXIAODOU_architectureOFXIAODOUIS
signalcnt:
std_logic_vector(3downto0);
BEGIN
process(clk)
begin
ifrising_edge(clk)then
ifrst_key='1'then
cnt<="0000";
rst_time<='1';
else
ifcnt="1001"then
rst_time<='0';
cnt<=cnt;
else
cnt<=cnt+1;
rst_time<='1';
endif;
endif;
endif;
endprocess;
ENDXIAODOU_architecture;
三:
按键处理信号
set键用来检测设置按键,第一次按下,为设置,第二次按下,为取消按键。
position为位置选择,按下一次选择第一个,按下二次为第二次,以此类推。
其余按键正常输出。
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;
ENTITYANJIANCHULIIS
PORT
(
clk:
INSTD_LOGIC;
rst:
INSTD_LOGIC;
set:
INSTD_LOGIC;
add:
INSTD_LOGIC;
position:
INSTD_LOGIC;
set_out:
OUTSTD_LOGIC;
rst_out:
OUTSTD_LOGIC;
add_out:
OUTSTD_LOGIC;
position1:
OUTSTD_LOGIC;
position2:
OUTSTD_LOGIC;
position3:
OUTSTD_LOGIC;
position4:
OUTSTD_LOGIC
);
ENDANJIANCHULI;
ARCHITECTUREANJIANCHULI_architectureOFANJIANCHULIIS
signalcnt:
std_logic_vector(1downto0);
signalcnt1:
std_logic_vector(1downto0);
begin
process(set)
begin
ifset'eventandset='0'then
cnt<=cnt+1;
endif;
endprocess;
set_out<='0'whencnt(0)='0'
else'1'whencnt(0)='0'
else'0';
process(position)
begin
ifposition'eventandposition='0'then
cnt1<=cnt1+1;
endif;
casecnt1is
when"00"=>position1<='0';position2<='1';position3<='1';position4<='1';
when"01"=>position1<='1';position2<='0';position3<='1';position4<='1';
when"10"=>position1<='1';position2<='1';position3<='0';position4<='1';
when"11"=>position1<='1';position2<='1';position3<='1';position4<='0';
whenothers=>null;
endcase;
endprocess;
process(clk)
begin
ifrising_edge(clk)then
rst_out<=rst;
add_out<=add;
endif;
endprocess;
ENDANJIANCHULI_architecture;
四:
计数十
十进制计数为时钟个位计数,自动计数满10,CY进1给六进制模块。
手动设置时,不进位
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;
ENTITYJISHUSHIIS
PORT
(
clk:
INSTD_LOGIC;
rst:
INSTD_LOGIC;
set:
INSTD_LOGIC;
add:
INSTD_LOGIC;
position:
INSTD_LOGIC;
dataout:
OUTSTD_LOGIC_VECTOR(3downto0);
os:
OUTSTD_LOGIC
);
ENDJISHUSHI_vhd;
ARCHITECTUREJISHUSHI_vhd_architectureOFJISHUSHI_vhdIS
signalbuffer_os:
std_logic;
signaladder_buffer:
std_logic_vector(3downto0);
signaladd_cnt:
std_logic_vector(3downto0);
BEGIN
buffer_os<='0'whenset='0'
elseclk;
process(set,position,buffer_os)
begin
ifrst='0'then
adder_buffer<="0000";
elsifset='0'andposition='0'then
adder_buffer<=add_cnt;
elsifrising_edge(buffer_os)then
ifadder_buffer="1001"then
adder_buffer<="0000";
os<='1';
else
adder_buffer<=adder_buffer+1;
os<='0';
endif;
endif;
endprocess;
dataout<=adder_buffer;
process(add)
begin
ifadd'eventandadd='0'then
ifadd_cnt="1001"then
add_cnt<="0000";
else
add_cnt<=add_cnt+1;
endif;
endif;
endprocess;
ENDJISHUSHI_vhd_architecture;
五:
计数六
六进制计数为时钟个位计数,自动计数满5,CY进1给十进制模块。
手动设置时,不进位
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;
ENTITYJISHULIU_vhdIS
PORT
(
clk:
INSTD_LOGIC;
set:
INSTD_LOGIC;
add:
INSTD_LOGIC;
position:
INSTD_LOGIC;
rst:
INSTD_LOGIC;
dataout:
OUTSTD_LOGIC_VECTOR(3downto0);
os:
OUTSTD_LOGIC
);
ENDJISHULIU_vhd;
ARCHITECTUREJISHULIU_vhd_architectureOFJISHULIU_vhdIS
signalbuffer_os:
std_logic;
signaladder_buffer:
std_logic_vector(3downto0);
signaladd_cnt:
std_logic_vector(3downto0);
BEGIN
buffer_os<='0'whenset='0'
elseclk;
process(buffer_os,rst,set,position)
begin
ifrst='0'then
adder_buffer<="0000";
elsifset='0'andposition<='0'then
adder_buffer<=add_cnt;
elsifrising_edge(buffer_os)then
ifadder_buffer="0101"then
adder_buffer<="0000";
os<='1';
else
adder_buffer<=adder_buffer+1;
os<='0';
endif;
endif;
endprocess;
dataout<=adder_buffer;
process(add)
begin
ifadd'eventandadd='0'then
ifadd_cnt="0101"then
add_cnt<="0000";
else
add_cnt<=add_cnt+1;
endif;
endif;
endprocess;
ENDJISHULIU_vhd_architecture;
六:
译码
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;
ENTITYcode_moduleIS
--{{ALTERA_IO_BEGIN}}DONOTREMOVETHISLINE!
PORT
(
datain:
INSTD_LOGIC_VECTOR(3downto0);
dataout:
OUTSTD_LOGIC_VECTOR(6downto0)
);
ENDcode_module;
ARCHITECTUREcode_module_architectureOFcode_moduleIS
BEGIN
process(datain)
begin
casedatainis
when"0000"=>dataout<="0000001";
when"0001"=>dataout<="1001111";
when"0010"=>dataout<="0010010";
when"0011"=>dataout<="0000110";
when"0100"=>dataout<="1001100";
when"0101"=>dataout<="0100100";
when"0110"=>dataout<="0100000";
when"0111"=>dataout<="0001111";
when"1000"=>dataout<="0000000";
when"1001"=>dataout<="0000100";
whenothers=>null;
endcase;
endprocess;
ENDcode_module_architecture;
七:
闪烁
当position为0时,让此数码管闪烁,当set和position都为1时,正常显示。
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;
ENTITYFLASH_vhdIS
PORT
(
clk:
INSTD_LOGIC;
clk_syn:
INSTD_LOGIC;
set:
INSTD_LOGIC;
position:
INSTD_LOGIC;
datain:
INSTD_LOGIC_VECTOR(6downto0);
dataout:
OUTSTD_LOGIC_VECTOR(6downto0)
);
ENDFLASH_vhd;
ARCHITECTUREFLASH_vhd_architectureOFFLASH_vhdIS
begin
process(set,position,clk)
begin
ifrising_edge(clk_syn)then
ifset='0'andposition='0'then
ifclk='1'then
dataout<=datain;
else
dataout<="1111111";
endif;
else
dataout<=datain;
endif;
endif;
endprocess;
ENDFLASH_vhd_architecture;