vhdl考试时钟.docx

1、vhdl考试时钟实验报告应用技术一班朱晓园，汪仙仙，张明星，胡亚洲一:分频模块定义clk为时钟输入引脚。输入20MHZ的频率。定义一个clk1hz分频和ckl100HZ分频。LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTITY FENPIN IS PORT ( clk : IN STD_LOGIC; oclk : OUT STD_LOGIC; oclk100hz : OUT STD_LOGIC ); END FENPIN;ARCHI

2、TECTURE FENPIN _architecture OF FENPIN ISBEGINprocess(clk)variable cnt :integer range 0 to 20000000;beginif rising_edge(clk) then cnt:=cnt+1; if cnt=10000000 then oclk=1; else if cnt=20000000 then cnt:=0; oclk=0; end if; end if;end if; end process;process(clk)variable cnt1 :integer range 0 to 200000

3、00; beginif rising_edge(clk) then if cnt1=200000 then cnt1:=0; oclk100hz=1; else cnt1:=cnt1+1; oclk100hz=0; end if; end if;end process;END FENPIN _architecture;二：按键消抖因为机械键盘存在抖动现象，所以需要用延时，软件去抖。这里用100HZ的频率，一旦出现低电平，就计数10次，一共100MS，然后再次检测，如果仍为低，就输出0信号。LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std

4、_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTITY XIAODOU ISPORT ( clk : IN STD_LOGIC; rst_key : IN STD_LOGIC; set_key : IN STD_LOGIC; position : IN STD_LOGIC; addup : IN STD_LOGIC; position_s : IN STD_LOGIC; addup_time : IN STD_LOGIC; rst_time : OUT STD_LOGIC; set_time : OUT STD_LOGIC ); END

5、XIAODOU;ARCHITECTURE XIAODOU_architecture OF XIAODOU ISsignal cnt:std_logic_vector(3 downto 0); BEGINprocess(clk)beginif rising_edge(clk) thenif rst_key=1thencnt=0000;rst_time=1;elseif cnt=1001 thenrst_time=0;cnt=cnt;elsecnt=cnt+1;rst_time=1;end if;end if;end if;end process;END XIAODOU_architecture;

6、三：按键处理信号set键用来检测设置按键，第一次按下，为设置，第二次按下，为取消按键。position为位置选择，按下一次选择第一个，按下二次为第二次，以此类推。其余按键正常输出。LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTITY ANJIANCHULI IS PORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; set : IN STD_LOGIC; add : IN STD_LOGIC;

7、 position : IN STD_LOGIC; set_out : OUT STD_LOGIC; rst_out : OUT STD_LOGIC; add_out : OUT STD_LOGIC; position1 : OUT STD_LOGIC; position2 : OUT STD_LOGIC; position3 : OUT STD_LOGIC; position4 : OUT STD_LOGIC );END ANJIANCHULI;ARCHITECTURE ANJIANCHULI_architecture OF ANJIANCHULI ISsignal cnt: std_log

8、ic_vector(1 downto 0); signal cnt1: std_logic_vector(1 downto 0); beginprocess(set)beginif setevent and set=0thencnt=cnt+1;end if;end process;set_out=0when cnt (0)=0 else1when cnt (0)=0 else0;process(position)beginif positionevent and position =0thencnt1position1=0;position2=1;position3=1;position4p

9、osition1=1;position2=0;position3=1;position4position1=1;position2=1;position3=0;position4position1=1;position2=1;position3=1;position4null;end case;end process;process(clk)beginif rising_edge(clk)thenrst_out=rst;add_out=add;end if;end process; END ANJIANCHULI_architecture;四：计数十十进制计数为时钟个位计数，自动计数满10，C

10、Y进1给六进制模块。手动设置时，不进位LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTITY JISHUSHI ISPORT ( clk : IN STD_LOGIC; rst : IN STD_LOGIC; set : IN STD_LOGIC; add : IN STD_LOGIC; position : IN STD_LOGIC; dataout : OUT STD_LOGIC_VECTOR(3 downto 0); os :

11、OUT STD_LOGIC ); END JISHUSHI_vhd;ARCHITECTURE JISHUSHI_vhd_architecture OF JISHUSHI_vhd ISsignal buffer_os:std_logic;signal adder_buffer:std_logic_vector(3 downto 0);signal add_cnt:std_logic_vector(3 downto 0);BEGINbuffer_os=0 when set=0 else clk;process(set,position,buffer_os)begin if rst=0 then a

12、dder_buffer=0000; elsif set=0 and position=0 then adder_buffer=add_cnt; elsif rising_edge(buffer_os) then if adder_buffer=1001 then adder_buffer=0000; os=1; else adder_buffer=adder_buffer+1; os=0; end if;end if;end process;dataout=adder_buffer;process(add)begin if addevent and add=0 then if add_cnt=

13、1001 then add_cnt=0000;else add_cnt=add_cnt+1; end if;end if;end process;END JISHUSHI_vhd_architecture;五：计数六六进制计数为时钟个位计数，自动计数满5，CY进1给十进制模块。手动设置时，不进位LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTITY JISHULIU_vhd ISPORT ( clk : IN STD_LOGIC; s

14、et : IN STD_LOGIC; add : IN STD_LOGIC; position : IN STD_LOGIC; rst : IN STD_LOGIC; dataout : OUT STD_LOGIC_VECTOR(3 downto 0); os : OUT STD_LOGIC ); END JISHULIU_vhd;ARCHITECTURE JISHULIU_vhd_architecture OF JISHULIU_vhd ISsignal buffer_os :std_logic;signal adder_buffer :std_logic_vector(3 downto 0

15、);signal add_cnt: std_logic_vector(3 downto 0);BEGINbuffer_os=0 when set=0 else clk;process(buffer_os,rst,set,position)begin if rst=0 then adder_buffer=0000; elsif set=0 and position=0 then adder_buffer=add_cnt; elsif rising_edge(buffer_os) then if adder_buffer=0101 then adder_buffer=0000; os=1; els

16、e adder_buffer=adder_buffer+1; os=0;end if;end if;end process;dataout=adder_buffer;process(add)beginif add event and add=0 then if add_cnt=0101 then add_cnt=0000; else add_cntdataoutdataoutdataoutdataoutdataoutdataoutdataoutdataoutdataoutdataoutnull;end case;end process;END code_module_architecture;

17、七：闪烁当position为0时，让此数码管闪烁，当set和position都为1时，正常显示。LIBRARY ieee;USE ieee.std_logic_1164.all;USE ieee.std_logic_arith.all;USE ieee.std_logic_unsigned.all;ENTITY FLASH_vhd ISPORT ( clk : IN STD_LOGIC; clk_syn : IN STD_LOGIC; set : IN STD_LOGIC; position : IN STD_LOGIC; datain : IN STD_LOGIC_VECTOR(6 down

18、to 0); dataout : OUT STD_LOGIC_VECTOR(6 downto 0) ); END FLASH_vhd;ARCHITECTURE FLASH_vhd _architecture OF FLASH_vhd ISbeginprocess(set,position,clk)beginif rising_edge(clk_syn) then if set=0 and position=0 then if clk=1 then dataout=datain; else dataout=1111111; end if; else dataout = datain; end if;end if;end process; END FLASH_vhd_architecture;