设计一个电子时钟要求可以显示时分秒用户可以设置时间.docx
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设计一个电子时钟要求可以显示时分秒用户可以设置时间
EDA课程设计-电子钟
一、设计要求
1、基本功能要求：
设计一个电子时钟，要求可以显示时、分、秒，用户可以设置时间。
扩展功能要求：
2、跑表功能，闹钟功能，调整数码管的亮度。
二、系统结构
控制键—jian5、jian4、jian7、jian8：
数码管显示段选信号输出sg：
——选择6位数码管中的某一个显示数据；
发光二极管控制信号输出—led（7~0）
闹钟声音输出—speaker
通过一个10M信号分出各种所需频率
功能介绍
运行后，选择模式7，8位数码管分显示时间的时、分、秒，当前为模式0：
时间显示模式，按键7为模式选择键，按下按键7，系统进入模式1，第二次按下为模式2，设置时间模式，第三次按下为跑表模式，第四次为闹钟设置模式，第五次为亮度调节模式：
设置时间模式，按键4控制更改数码管的位，按键5控制选中数码管的数值，时间设置完成后，按键按键8，设置时间会保存住，并在模式0中显示；系统进入模式2：
秒表模式，按键4为开始/结束键，按键5为清零键；系统进入模式3：
闹钟设置模式，相关设置与模式1相同，当当前时间与闹钟设置时间相同时，喇叭就会响；系统进入模式4:
亮度调节模式，通过按键4设置亮度，共三种亮度；再按下按键7，系统又会进入模式0。
4、RTL图
三、VHDL源程序
1、libraryieee;--通过10M分出所需频率
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityfenpinis
port（
clk_10M:
instd_logic;
clk_10000:
outstd_logic;
clk_100:
outstd_logic;
clk_1:
outstd_logic
）;
endentity;
architecturesub1offenpinis
signalQ_1:
std_logic_vector（8downto0）;
signalQ_2:
std_logic_vector（6downto0）;
signalQ_3:
std_logic_vector（6downto0）;
signalclk10000:
std_logic;
signalclk100:
std_logic;
signalclk1:
std_logic;
begin
process（clk_10M）
begin
ifclk_10M'eventandclk_10M='1'then
ifQ_1=500then
Q_1<="000000000";
clk10000<=notclk10000;
ifQ_2=100then
Q_2<="0000000";
clk100<=notclk100;
ifQ_3=100then
Q_3<="0000000";
clk1<=notclk1;
elseQ_3<=Q_3+1;
endif;
elseQ_2<=Q_2+1;
endif;
elseQ_1<=Q_1+1;
endif;
endif;
endprocess;
clk_10000<=clk10000;
clk_100<=clk100;
clk_1<=clk1;
endsub1;
2、libraryieee;--扫描数码管
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entityxianshiis
port（clk_10000:
instd_logic;
jian4:
instd_logic;
moshi:
inintegerrange0to4;
a0,a1,a3,a4,a6,a7:
inintegerrange0to9;
sg11:
outstd_logic_vector（6downto0）;
bt11:
outstd_logic_vector（7downto0））;
end;
architectureoneofxianshiis
signalcnt8:
std_logic_vector（2downto0）;
signala:
integerrange0to15;
signallight:
std_logic;
signalflash:
integerrange0to2;
signalcount1,count2:
integerrange0to10;
begin
p1:
process（cnt8,light,a0,a1,a3,a4,a6,a7）
begin
casecnt8is
when"000"=>bt11<="0000000"&（light）;a<=a0;
when"001"=>bt11<="000000"&（light）&'0';a<=a1;
when"010"=>bt11<="00000"&（light）&"00";a<=15;
when"011"=>bt11<="0000"&（light）&"000";a<=a3;
when"100"=>bt11<="000"&（light）&"0000";a<=a4;
when"101"=>bt11<="00"&（light）&"00000";a<=15;
when"110"=>bt11<='0'&（light）&"000000";a<=a6;
when"111"=>bt11<=（light）&"0000000";a<=a7;
whenothers=>null;
endcase;
endprocessp1;
p2:
process（clk_10000）
begin
ifclk_10000'eventandclk_10000='1'thencnt8<=cnt8+1;
endif;
endprocessp2;
p3:
process（a）
begin
caseais
when0=>sg11<="0111111";
when1=>sg11<="0000110";
when2=>sg11<="1011011";
when3=>sg11<="1001111";
when4=>sg11<="1100110";
when5=>sg11<="1101101";
when6=>sg11<="1111101";
when7=>sg11<="0000111";
when8=>sg11<="1111111";
when9=>sg11<="1101111";
when10=>sg11<="1110111";
when11=>sg11<="1111100";
when12=>sg11<="0111001";
when13=>sg11<="1011110";
when14=>sg11<="1111001";
when15=>sg11<="1000000";
whenothers=>null;
endcase;
endprocessp3;
process（jian4,moshi）
begin
ifmoshi=4then
ifjian4'eventandjian4='1'then
ifflash=2then
flash<=0;
elseflash<=flash+1;
endif;
endif;
endif;
endprocess;
process（clk_10000,flash）
begin
ifclk_10000'eventandclk_10000='1'then
caseflashis
when0=>light<='1';
when1=>ifcount1=2then
count1<=0;light<='1';
elsecount1<=count1+1;light<='0';
endif;
when2=>ifcount2=4then
count2<=0;light<='1';
elsecount2<=count2+1;light<='0';
endif;
endcase;
endif;
endprocess;
end;
3、libraryieee;--跑表开始暂停
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitypaobiaois
port（clk_1:
instd_logic;
jian8:
instd_logic;
shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:
inintegerrange0to9;
shishi2,shige2,fenshi2,fenge2,miaoshi2,miaoge2:
outintegerrange0to9）;
endentity;
architecturebhvofpaobiaois
signalshi:
integerrange0to100;
signalfen:
integerrange0to100;
signalmiao:
integerrange0to100;
begin
process（clk_1,jian8,shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1）
begin
ifjian8='1'then
shi<=shishi1*10+shige1;
fen<=fenshi1*10+fenge1;
miao<=miaoshi1*10+miaoge1;
elsifclk_1'eventandclk_1='1'then
ifmiao=59then
miao<=0;
fen<=fen+1;
elsiffen>59then
fen<=0;
shi<=shi+1;
elsifshi>23then
shi<=0;
elsemiao<=miao+1;
endif;
endif;
endprocess;
miaoge2<=miaorem10;
miaoshi2<=miao/10;
fenge2<=fenrem10;
fenshi2<=fen/10;
shige2<=shirem10;
shishi2<=shi/10;
end;
4、libraryieee;--设置当前时间
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitysettimeis
port（moshi:
inintegerrange0to4;
jian4,jian5:
instd_logic;
shishi,shige,fenshi,fenge,miaoshi,miaoge:
outintegerrange0to9）;
endentity;
architecturebavofsettimeis
signala:
integerrange0to5;
signalshishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:
integerrange0to9;
begin
process（moshi,jian4）
begin
ifmoshi=1then
ifjian4'eventandjian4='1'then
ifa<5then
a<=a+1;
elsea<=0;
endif;
endif;
endif;
endprocess;
process（moshi,a,jian5）
begin
ifmoshi=1then
ifa=0then
ifjian5'eventandjian5='1'then
ifmiaoge1=9then
miaoge1<=0;
elsemiaoge1<=miaoge1+1;
endif;
endif;
endif;
ifa=1then
ifjian5'eventandjian5='1'then
ifmiaoshi1=5then
miaoshi1<=0;
elsemiaoshi1<=miaoshi1+1;
endif;
endif;
endif;
ifa=2then
ifjian5'eventandjian5='1'then
iffenge1=9then
fenge1<=0;
elsefenge1<=fenge1+1;
endif;
endif;
endif;
ifa=3then
ifjian5'eventandjian5='1'then
iffenshi1=5then
fenshi1<=0;
elsefenshi1<=fenshi1+1;
endif;
endif;
endif;
ifa=4then
ifjian5'eventandjian5='1'then
ifshige1=9then
shige1<=0;
elseshige1<=shige1+1;
endif;
endif;
endif;
ifa=5then
ifjian5'eventandjian5='1'then
ifshishi1=2then
shishi1<=0;
elseshishi1<=shishi1+1;
endif;
endif;
endif;
endif;
endprocess;
miaoge<=miaoge1;
miaoshi<=miaoshi1;
fenge<=fenge1;
fenshi<=fenshi1;
shige<=shige1;
shishi<=shishi1;
end;
5、libraryieee;--秒表功能
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymiaobiaois
port（clk_100:
instd_logic;
moshi:
inintegerrange0to4;
jian5,jian4:
instd_logic;
fenshi,fenge,miaoshi,miaoge,xmiaoshi,xmiaoge:
outintegerrange0to9）;
endentity;
architecturebhvofmiaobiaois
signalfen,miao,xmiao:
integerrange0to99;
signalstart:
std_logic:
='0';
signalreset:
std_logic:
='0';
begin
process（clk_100,jian5,jian4,moshi,reset,start）
begin
ifmoshi=2then
ifreset='1'then
fen<=0;
miao<=0;
xmiao<=0;
elsifstart='1'then
elsifclk_100'eventandclk_100='1'then
ifxmiao=99then
xmiao<=0;
miao<=miao+1;
elsifmiao>59then
miao<=0;
fen<=fen+1;
elsiffen>23then
fen<=0;
elsexmiao<=xmiao+1;
endif;
endif;
endif;
endprocess;
process（jian4,start）
begin
ifjian4'eventandjian4='1'then
start<=notstart;
elsestart<=start;
endif;
endprocess;
process（jian5,reset）
begin
ifjian5'eventandjian5='1'then
reset<=notreset;
elsereset<=reset;
endif;
endprocess;
xmiaoge<=xmiaorem10;
xmiaoshi<=xmiao/10;
miaoge<=miaorem10;
miaoshi<=miao/10;
fenge<=fenrem10;
fenshi<=fen/10;
end;
6、libraryieee;--设置闹钟时间
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitynaozhongsetis
port（moshi:
inintegerrange0to4;
jian4,jian5:
instd_logic;
shishi,shige,fenshi,fenge,miaoshi,miaoge:
outintegerrange0to9）;
endentity;
architecturebavofnaozhongsetis
signala:
integerrange0to5;
signalfenshi1,fenge1,miaoge1:
integerrange0to9;
signalshishi1:
integerrange0to9:
=1;
signalshige1:
integerrange0to9:
=2;
signalmiaoshi1:
integerrange0to9:
=0;
begin
process（moshi,jian4）
begin
ifmoshi=3then
ifjian4'eventandjian4='1'then
ifa<5then
a<=a+1;
elsea<=0;
endif;
endif;
endif;
endprocess;
process（moshi,a,jian5）
begin
ifmoshi=3then
ifa=0then
ifjian5'eventandjian5='1'then
ifmiaoge1=9then
miaoge1<=0;
elsemiaoge1<=miaoge1+1;
endif;
endif;
endif;
ifa=1then
ifjian5'eventandjian5='1'then
ifmiaoshi1=5then
miaoshi1<=0;
elsemiaoshi1<=miaoshi1+1;
endif;
endif;
endif;
ifa=2then
ifjian5'eventandjian5='1'then
iffenge1=9then
fenge1<=0;
elsefenge1<=fenge1+1;
endif;
endif;
endif;
ifa=3then
ifjian5'eventandjian5='1'then
iffenshi1=5then
fenshi1<=0;
elsefenshi1<=fenshi1+1;
endif;
endif;
endif;
ifa=4then
ifjian5'eventandjian5='1'then
ifshige1=9then
shige1<=0;
elseshige1<=shige1+1;
endif;
endif;
endif;
ifa=5then
ifjian5'eventandjian5='1'then
ifshishi1=2then
shishi1<=0;
elseshishi1<=shishi1+1;
endif;
endif;
endif;
endif;
endprocess;
miaoge<=miaoge1;
miaoshi<=miaoshi1;
fenge<=fenge1;
fenshi<=fenshi1;
shige<=shige1;
shishi<=shishi1;
end;
7、libraryieee;--闹钟喇叭输出
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitynaozhongspeakeris
port（clk_100:
instd_logic;
shishi1,shige1,fenshi1,fenge1,miaoshi1,miaoge1:
inintegerrange0to9;
shishi2,shige2,fenshi2,fenge2,miaoshi2
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