实验二4位十进制计数器的设计.docx
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实验二4位十进制计数器的设计
实验二4位十进制计数器的设计
一、实验目的:
1、深入理解信号和变量的区别;
2、深入理解并行语句和顺序语句的区别;
3、深入理解异步和同步的概念;
4、掌握计数器的设计方法;
5、能会看最大系统运行频率和资源使用报告。
二、实验原理:
四位十进制计数器程序A:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybcd_counteris
port
(
clk:
instd_logic;
reset:
instd_logic;
co:
outstd_logic;
q:
outstd_logic_vector(3downto0)
);
endentity;
architecturebevofbcd_counteris
begin
process(clk)
variablecnt:
std_logic_vector(3downto0);
begin
if(rising_edge(clk))then
ifreset='1'then
cnt:
="0000";
else
ifcnt<9then
cnt:
=cnt+"0001";
else
cnt:
="0000";
co<='1';
endif;
endif;
endif;
q<=cnt;
endprocess;
endbev;
四位十进制计数器程序B:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybcd_counter2is
port
(
clk:
instd_logic;
reset:
instd_logic;
co:
outstd_logic;
q:
outstd_logic_vector(3downto0)
);
endentity;
architecturebevofbcd_counter2is
signalcnt:
std_logic_vector(3downto0);
begin
process(clk)
begin
if(rising_edge(clk))then
ifreset='1'then
cnt<="0000";
else
ifcnt<9then
cnt<=cnt+"0001";
else
cnt<="0000";
co<='1';
endif;
endif;
endif;
endprocess;
q<=cnt;
endbev;
四位十进制计数器程序C:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitybcd_counter3is
port
(
clk:
instd_logic;
reset:
instd_logic;
co:
outstd_logic;
q:
outstd_logic_vector(3downto0)
);
endentity;
architecturebevofbcd_counter3is
signalcnt:
std_logic_vector(3downto0);
begin
process(clk)
begin
ifreset='1'then
cnt<="0000";
elsif(rising_edge(clk))then
ifcnt<9then
cnt<=cnt+"0001";
else
cnt<="0000";
co<='1';
endif;
endif;
endprocess;
q<=cnt;
endbev;
三、实验内容:
1、资源使用情况和最大运行频率:
程序
使用逻辑单元数
使用寄存器数
最大运行频率(MHz)
(slow1200mV85CModel)
A
7
4
452.49
B
7
4
452.49
C
4
4
710.73
2、RTL视图和TechnologyMap视图
程序A
程序B
程序C
3、testbench文件
程序A
LIBRARYaltera;
LIBRARYcycloneiii;
LIBRARYieee;
USEaltera.altera_primitives_components.all;
USEcycloneiii.cycloneiii_components.all;
USEieee.std_logic_1164.all;
ENTITYbcd_counter_tbIS
END;
ARCHITECTUREbcd_counter_tb_archOFbcd_counter_tbIS
SIGNALq:
std_logic_vector(3downto0);
SIGNALclk:
STD_LOGIC:
='0';
SIGNALco:
STD_LOGIC;
SIGNALreset:
STD_LOGIC:
='0';
COMPONENTbcd_counter
PORT(
q:
outstd_logic_vector(3downto0);
clk:
inSTD_LOGIC;
co:
outSTD_LOGIC;
reset:
inSTD_LOGIC);
ENDCOMPONENT;
BEGIN
DUT:
bcd_counter
PORTMAP(
q=>q,
clk=>clk,
co=>co,
reset=>reset);
reset<='1'after380ns,
'0'after550ns;
clk<=notclkafter100ns;
END;
程序B
LIBRARYaltera;
LIBRARYcycloneiii;
LIBRARYieee;
USEaltera.altera_primitives_components.all;
USEcycloneiii.cycloneiii_components.all;
USEieee.std_logic_1164.all;
ENTITYbcd_counter2_tbIS
END;
ARCHITECTUREbcd_counter2_tb_archOFbcd_counter2_tbIS
SIGNALq:
std_logic_vector(3downto0);
SIGNALclk:
STD_LOGIC:
='0';
SIGNALco:
STD_LOGIC;
SIGNALreset:
STD_LOGIC:
='0';
COMPONENTbcd_counter2
PORT(
q:
outstd_logic_vector(3downto0);
clk:
inSTD_LOGIC;
co:
outSTD_LOGIC;
reset:
inSTD_LOGIC);
ENDCOMPONENT;
BEGIN
DUT:
bcd_counter2
PORTMAP(
q=>q,
clk=>clk,
co=>co,
reset=>reset);
reset<='1'after150ns,
'0'after450ns;
clk<=notclkafter100ns;
END;
程序C
LIBRARYaltera;
LIBRARYcycloneiii;
LIBRARYieee;
USEaltera.altera_primitives_components.all;
USEcycloneiii.cycloneiii_components.all;
USEieee.std_logic_1164.all;
ENTITYbcd_counter3_tbIS
END;
ARCHITECTUREbcd_counter3_tb_archOFbcd_counter3_tbIS
SIGNALq:
std_logic_vector(3downto0);
SIGNALclk:
STD_LOGIC:
='0';
SIGNALco:
STD_LOGIC;
SIGNALreset:
STD_LOGIC:
='0';
COMPONENTbcd_counter3
PORT(
q:
outstd_logic_vector(3downto0);
clk:
inSTD_LOGIC;
co:
outSTD_LOGIC;
reset:
inSTD_LOGIC);
ENDCOMPONENT;
BEGIN
DUT:
bcd_counter3
PORTMAP(
q=>q,
clk=>clk,
co=>co,
reset=>reset);
clk<=notclkafter100ns;
reset<='1'after50ns,
'0'after350ns;
END;
4、最终的时序波形及输出延时
程序A时序仿真波形
程序A输出延时的波形及时间
延时7ns
程序B时序仿真波形
程序B输出延时的波形及时间
延时7ns
程序C时序仿真波形
程序C输出延时的波形及时间
输出延时5ns
5、重新设定clk的时钟频率大于1中的最大工作频率时观察时序仿真波形,并与4中的仿真波形对比,说明差别的原因。
程序A时序仿真波形
程序B时序仿真波形
程序C时序仿真波形
不同的原因:
超出最大工作频率
四、思考题:
1、对比三个程序中的复位实现的异同(同步与异步)?
2、对比三个程序的仿真波形,指出它们的异同,并阐述原因?
3、对比三个程序,阐述信号和变量的区别?
4、对比三个程序,阐述并行语句和顺序语句的区别?