基于VHDL语言的EDA实验报告.docx
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基于VHDL语言的EDA实验报告
E
D
A
实
验
报
告
班级：
电科五班
姓名：
张红义
学号:
1008101143
半加器
全加器
十进制计数器
实验源码：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYCNT10IS
PORT（CLK,RST,EN,LOAD:
INSTD_LOGIC;
DATA:
INSTD_LOGIC_VECTOR（3DOWNTO0）;
DOUT:
OUTSTD_LOGIC_VECTOR（3DOWNTO0）;
COUT:
OUTSTD_LOGIC）;
ENDCNT10;
ARCHITECTUREbehavOFCNT10IS
BEGIN
PROCESS（CLK,RST,EN,LOAD）
VARIABLEQ:
STD_LOGIC_VECTOR（3DOWNTO0）;
BEGIN
IFRST='0'THENQ:
=（OTHERS=>'0'）;
ELSIFCLK'EVENTANDCLK='1'THEN
IFEN='1'THEN
IF（LOAD='0'）THENQ:
=DATA;ELSE
IFQ<9THENQ:
=Q+1;
ELSEQ:
=（OTHERS=>'0'）;
ENDIF;
ENDIF;
ENDIF;
ENDIF;
IFQ="1001"THENCOUT<='1';
ELSECOUT<='0';ENDIF;
DOUT<=Q;
ENDPROCESS;
ENDbehav;
仿真波形：
封装图：
3-8译码器
实验源码：
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITYYM38IS
PORT（A:
INSTD_LOGIC_VECTOR（2DOWNTO0）;
EN:
INSTD_LOGIC;
Y:
OUTSTD_LOGIC_VECTOR（7DOWNTO0））;
ENDYM38;
ARCHITECTUREBEHAVOFYM38IS
SIGNALCLK:
STD_LOGIC_VECTOR（3DOWNTO0）;
BEGIN
CLK<=A&EN;
PROCESS（CLK）
BEGIN
CASECLKIS
WHEN"0001"=>Y<="00000001";
WHEN"0011"=>Y<="00000010";
WHEN"0101"=>Y<="00000100";
WHEN"0111"=>Y<="00001000";
WHEN"1001"=>Y<="00010000";
WHEN"1011"=>Y<="00100000";
WHEN"1101"=>Y<="01000000";
WHEN"1111"=>Y<="10000000";
WHENOTHERS=>Y<="00000000";
ENDCASE;
ENDPROCESS;
ENDBEHAV;
仿真波形：
封装图：
MEALY型有限状态机
实验源码:
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
ENTITYMEALY1IS
PORT（CLK,DIN1,DIN2,RST:
INSTDD_LOGIC;
Q:
OUTSTD_LOGIC_VECTOR（4DOWNTO0））;
ENDMEALY1;
ARCHITECTUREBEHAVOFMEALY1IS
TYPESTATESIS（ST0,ST1,ST2,ST3,ST4）;
SIGNALPST:
STATES;
BEGIN
REGCOM:
PROCESS（CLK,RST,PST,DIN1）BEGIN
IFRST='1'THENPST<=ST0;ELSIFRISING_EDGE（CLK）THEN
CASEPSTIS
WHENST0=>IFDIN1='1'THENPST<=ST1;ELSEPST<=ST0;ENDIF;
WHENST1=>IFDIN1='1'THENPST<=ST2;ELSEPST<=ST1;ENDIF;
WHENST2=>IFDIN1='1'THENPST<=ST3;ELSEPST<=ST2;ENDIF;
WHENST3=>IFDIN1='1'THENPST<=ST4;ELSEPST<=ST3;ENDIF;
WHENST4=>IFDIN1='0'THENPST<=ST0;ELSEPST<=ST4;ENDIF;
WHENOTHERS=>PST<=ST0;
ENDCASE;ENDIF;
ENDPROCESSREGCOM:
;
COM:
PROCESS（PST,DIN2）BEGIN
CASEPSTIS
WHENST0=>IFDIN2='1'THENQ<="10000";ELSEQ<="01010";ENDIF;
WHENST1=>IFDIN2='0'THENQ<="10111";ELSEQ<="10100";ENDIF;
WHENST2=>IFDIN2='1'THENQ<="10101";ELSEQ<="10011";ENDIF;
WHENST3=>IFDIN2='0'THENQ<="11011";ELSEQ<="01001";ENDIF;
WHENST4=>IFDIN2='1'THENQ<="11101";ELSEQ<="01101";ENDIF;
WHENOTHERS=>Q<="00000";
ENDCASE;
ENDPROCESSCOM;
END;
跑马灯
实验源码：
Libraryieee;
useieee.std_logic_1164.all;
entitycyc_ledis
port（clr,clk:
instd_logic;
led1,led2,led3:
outstd_logic）;
end;
architectureaofcyc_ledis
typestatesis（s0,s1,s2,s3,s4,s5）;
signalq:
std_logic_vector（0to2）;
signalstate:
states;
begin
p1:
process（clk,clr）
begin
if（clr='0'）then
state<=s0;led1<='0';led2<='0';led3<='0';
elsif（clk'eventandclk='1'）then
casestateis
whens0=>state<=s1;led1<='1';led2<='0';led3<='0';
whens1=>state<=s2;led1<='0';led2<='1';led3<='0';
whens2=>state<=s3;led1<='0';led2<='1';led3<='0';
whens3=>state<=s4;led1<='0';led2<='0';led3<='1';
whens4=>state<=s5;led1<='0';led2<='0';led3<='1';
whens5=>state<=s0;led1<='0';led2<='0';led3<='1';
endcase;
endif;
endprocess;
end;
实验图：
LED数码管循环显示0～9
实验源码：
LIBRARYIEEE;
USEIEEE.std_logic_1164.all;
USEIEEE.std_logic_arith.all;
USEIEEE.std_logic_unsigned.all;
ENTITYxianshiIS
PORT（clk:
instd_logic;
Led7s:
outstd_logic_vector（6downto0））;
--sel:
outstd_logic_vector（1downto0））;
ENDENTITY;
ARCHITECTUREfuncOFxianshiIS
SIGNALfp,tmp:
std_logic;
SIGNALcount:
std_logic_vector（9downto0）;
SIGNALsl:
std_logic_vector（3downto0）;
--sl1:
std_logic_vector（1downto0）;
BEGIN
PROCESS（clk）
BEGIN
IF（clk'EVENTANDclk='1'）THEN
IF（count="1111100111"）THEN
count<=（OTHERS=>'0'）;
tmp<=NOTtmp;
ELSE
count<=count+1;
ENDIF;
ENDIF;
fp<=tmp;
ENDPROCESS;
counter1:
PROCESS（fp）
BEGIN
IF（fp'EVENTANDfp='1'）THEN
IF（sl="1001"）THENsl<="0000";
ELSEsl<=sl+1;
ENDIF;
ENDIF;
ENDPROCESS;
diplay:
PROCESS（sl）
BEGIN
CASEslIS
when"0000"=>led7s<="0111111";
when"0001"=>led7s<="0000110";
when"0010"=>led7s<="1011011";
when"0011"=>led7s<="1001111";
when"0100"=>led7s<="1100110";
when"0101"=>led7s<="1101101";
when"0110"=>led7s<="1111101";
when"0111"=>led7s<="0000111";
when"1000"=>led7s<="1111111";
when"1001"=>led7s<="1101111";
WHENOTHERS=>NULL;
ENDCASE;
ENDPROCESS;
ENDARCHITECTURE;
实验图：
16*16点阵显示_北京欢迎
实验源码：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitytest_led1is
port（clk:
instd_logic;
dotout:
outstd_logic_vector（15downto0）;--行驱动信号输出
selout:
outstd_logic_vector（3downto0））;--列选信号号输出
endtest_led1;
architecturebehaveoftest_led1is
signalcount:
std_logic_vector（11downto0）;
signalq:
std_logic_vector（10downto0）;
signalcnt16:
std_logic_vector（3downto0）;
signaldout:
std_logic_vector（15downto0）;
signala:
integerrange0to15;
signaltmp:
std_logic_vector（1downto0）:
="00";
begin
reg:
PROCESS（clk）
BEGIN
IF（clk'EVENTANDclk='1'）THEN
IF（count="111110100000"）THEN
count<=（OTHERS=>'0'）;
if（tmp="11"）thentmp<="00";
elsetmp<=tmp+1;
endif;
ELSE
count<=count+1;
ENDIF;
ENDIF;
ENDPROCESS;
p1:
process（cnt16）
begin
iftmp="00"then
casecnt16is
when"0000"=>dout<="0010000000000000";a<=0;
when"0001"=>dout<="0011000000100000";a<=1;
when"0010"=>dout<="0001100000100000";a<=2;
when"0011"=>dout<="0000100000100000";a<=3;
when"0100"=>dout<="0000010000100000";a<=4;
when"0101"=>dout<="0111111111111111";a<=5;
when"0110"=>dout<="0000000000000000";a<=6;
when"0111"=>dout<="0000000000000000";a<=7;--北
when"1000"=>dout<="0000000000000000";a<=8;
when"1001"=>dout<="0011111111111111";a<=9;
when"1010"=>dout<="0100000001000000";a<=10;
when"1011"=>dout<="0100000000100000";a<=11;
when"1100"=>dout<="0100000000011000";a<=12;
when"1101"=>dout<="0100000000001100";a<=13;
when"1110"=>dout<="0111100000001000";a<=14;
when"1111"=>dout<="0000000000000000";a<=15;
whenothers=>null;
endcase;
elsiftmp="01"then
casecnt16is
when"0000"=>dout<="0000000000000000";a<=0;
when"0001"=>dout<="0000000000000100";a<=1;
when"0010"=>dout<="0000000000000100";a<=2;
when"0011"=>dout<="0010000000000100";a<=3;
when"0100"=>dout<="0001000000000100";a<=4;
when"0101"=>dout<="0000100111110100";a<=5;
when"0110"=>dout<="0000000100010101";a<=6;
when"0111"=>dout<="1100000100010101";a<=7;--京
when"1000"=>dout<="1111110100010101";a<=8;
when"1001"=>dout<="0000000100010100";a<=9;
when"1010"=>dout<="0000000100010100";a<=10;
when"1011"=>dout<="0000100111110100";a<=11;
when"1100"=>dout<="0001000000000100";a<=12;
when"1101"=>dout<="0010000000000100";a<=13;
when"1110"=>dout<="0000000000000100";a<=14;
when"1111"=>dout<="0000000000000000";a<=15;
whenothers=>null;
endcase;
elsiftmp="10"
then
casecnt16is
when"0000"=>dout<="0000000000000000";a<=0;
when"0001"=>dout<="0000000000000000";a<=1;
when"0010"=>dout<="0000001000011000";a<=2;
when"0011"=>dout<="0000000100101000";a<=3;
when"0100"=>dout<="0000000001001000";a<=4;
when"0101"=>dout<="0000000010011000";a<=5;
when"0110"=>dout<="0000100100000100";a<=6;
when"0111"=>dout<="0000001000000011";a<=7;--欢
when"1000"=>dout<="0000000010000010";a<=8;
when"1001"=>dout<="0000000000100010";a<=9;
when"1010"=>dout<="0000000000001010";a<=10;
when"1011"=>dout<="0000000001000010";a<=11;
when"1100"=>dout<="0000000010000010";a<=12;
when"1101"=>dout<="0000000100001010";a<=13;
when"1110"=>dout<="0000001000000110";a<=14;
when"1111"=>dout<="0000000000000000";a<=15;
whenothers=>null;
endcase;
elsiftmp="11"
then
casecnt16is
when"0000"=>dout<="1000000000010010";a<=0;
when"0001"=>dout<="0111111111110100";a<=1;
when"0010"=>dout<="0010000000000000";a<=2;
when"0011"=>dout<="0100000000000000";a<=3;
when"0100"=>dout<="1000111111111100";a<=4;
when"0101"=>dout<="1000100000000010";a<=5;
when"0110"=>dout<="1000110000000010";a<=6;
when"0111"=>dout<="1000000000000000";a<=7;--迎
when"1000"=>dout<="1000000000000000";a<=8;
when"1001"=>dout<="1001111111111110";a<=9;
when"1010"=>dout<="1000000000000010";a<=10;
when"1011"=>dout<="1000100001000010";a<=11;
when"1100"=>dout<="1000111111110010";a<=12;
when"1101"=>dout<="1000000000000000";a<=13;
when"1110"=>dout<="1000000000000000";a<=14;
when"1111"=>dout<="0000000000000000";a<=15;
whenothers=>null;
endcase;
endif;
dotout<=dout;
endprocessp1;
p2:
process（clk）
begin
ifclk'eventandclk='1'thenq<=q+1;
endif;
cnt16<=q（3downto0）;
endprocessp2;
p3:
process（a）--4/16译码电路
begin
caseais
when0=>selout<="0000";
when1=>selout<="0001";
when2=>selout<="0010";
when3=>selout<="0011";
when4=>selout<="0100";
when5=>selout<="0101";
when6=>selout<="0110";
when7=>selout<="0111";
when8=>selout<="1000";
when9=>selout<="1001";
when10=>selout<="1010";
when11=>selout<="1011";
when12=>selout<="1100";
when13=>selout<="1101";
when14=>selout<="1110";
when15=>selout<="1111";
whenothers=>null;
endcase;
endprocessp3;
endbehave;
实验图：
16*16点阵显示_河南农大
实验源码：
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitytest
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