VHDL8位CPU设计包含程序.docx
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VHDL8位CPU设计包含程序
ComputerOrganizationandArchitecture
CourseDesign
TheExperimentReport
Of
CPU
I.Purpose
ThepurposeofthisprojectistodesignasimpleCPU(CentralProcessingUnit).ThisCPUhasbasicinstructionset,andwewillutilizeitsinstructionsettogenerateaverysimpleprogramtoverifyitsperformance.Forsimplicity,wewillonlyconsidertherelationshipamongtheCPU,registers,memoryandinstructionset.Thatistosayweonlyneedconsiderthefollowingitems:
Read/WriteRegisters,Read/WriteMemoryandExecutetheinstructions.
AtleastfourpartsconstituteasimpleCPU:
thecontrolunit,theinternalregisters,theALUandinstructionset,whicharethemainaspectsofourprojectdesignandwillbestudied.
II.InstructionSet
Single-addressinstructionformatisusedinoursimpleCPUdesign.Theinstructionwordcontainstwosections:
theoperationcode(opcode),whichdefinesthefunctionofinstructions(addition,subtraction,logicoperations,etc.);theaddresspart,inmostinstructions,theaddresspartcontainsthememorylocationofthedatumtobeoperated,wecalleditdirectaddressing.Insomeinstructions,theaddresspartistheoperand,whichiscalledimmediateaddressing.
Forsimplicity,thesizeofmemoryis256×16inthecomputer.Theinstructionwordhas16bits.Theopcodeparthas8bitsandaddressparthas8bits.TheinstructionwordformatcanbeexpressedinFigure1:
OPCODE
[15..0]
ADDRESS
[7..0]
Figure1theinstructionformat
TheopcodeoftherelevantinstructionsarelistedinTable1.
InTable1,thenotation[x]representsthecontentsofthelocationxinthememory.Forexample,theinstructionword00000011101110012(03B916)meansthattheCPUaddswordatlocationB916inmemoryintotheaccumulator(ACC);theinstructionword00000101000001112(050716)meansifthesignbitoftheACC(ACC[15])is0,theCPUwillusetheaddresspartoftheinstructionastheaddressofnextinstruction,ifthesignbitis1,theCPUwillincreasetheprogramcounter(PC)anduseitscontentastheaddressofthenextinstruction.
Table1Listofopcodeoftherelevantinstructions
INSTRUCTION
OPCODE
COMMENTS
STOREX
01H
ACC→[X]
LOADX
02H
[X]→ACC
ADDX
03H
ACC+[X]→ACC
SUBX
04H
ACC-[X]→ACC
JMPGZX
05H
IFACC>0THENX→PCELSEPC+1→PC
ANDX
06H
ACCand[X]→ACC
ORX
07H
ACCor[X]→ACC
NOTX
08H
Not[X]→ACC
SHIFTRX
09H
SHIFLACCtoRIGHT1bit,LogicShift
SHIFTLX
0AH
SHIFTACCtoLEFT1bit,LogicShift
MPYX
0BH
ACC×[X]→ACC
HALT
0CH
HALTAPROGRAM
Aprogramisdesignedtotesttheseinstructions:
Calculatethesumofallintegersfrom1to100.
(1),programmingwithClanguage:
sum=0;
temp=100;
loop:
sum=sum+temp;
temp=temp-1;
iftemp>=0gotoloop;
end
(2),AssumeintheRAM_DQ:
sumisstoredatlocationA4,
tempisstoredatlocationA3,
thecontentsoflocationA0is0,
thecontentsoflocationA1is1,
thecontentsoflocationA2is10010=6416.
WecantranslatetheaboveClanguageprogramwiththeinstructionslistedinTable1intotheinstructionprogramasshowninTable2.
Table2Exampleofaprogramtosumfrom1to100
ProgramwithC
Programwith
instructions
ContentsofRAM_DQinHEX
Address
Contents
sum=0;
LOADA0
00
02A0
STOREA4
01
01A4
temp=100
LOADA2
02
02A2
STOREA3
03
01A3
loop:
sum=sum+temp;
LOOP:
LOADA4
04
02A4
ADDA3
05
03A3
STOREA4
06
01A4
temp=temp-1;
LOADA3
07
02A3
SUBA1
08
04A1
STOREA3
09
01A3
iftemp>0gotoloop;
JMPGZLOOP
0A
0504
end;
HALT
0B
0C00
0C
…
…
A0
0000
A1
0001
A2
0064
A3
A4
…
…
III.InternalRegistersandMemory
MAR(MemoryAddressRegister)
MARcontainsthememorylocationofthewordtobereadfromthememoryorwrittenintothememory.Here,READoperationisdenotedastheCPUreadsfrommemory,andWRITEoperationisdenotedastheCPUwritestomemory.Inourdesign,MARhas8bitstoaccessoneof256addressesofthememory.
MBR(MemoryBufferRegister)
MBRcontainsthevaluetobestoredinmemoryorthelastvaluereadfrommemory.MBRisconnectedtotheaddresslinesofthesystembus.Inourdesign,MBRhas16Bits.
PC(ProgramCounter)
PCkeepstrackoftheinstructionstobeusedintheprogram.Inourdesign,PChas8bits.
IR(InstructionRegister)
IRcontainstheopcodepartofaninstruction.Inourdesign,IRhas8bits.
BR(BufferRegister)
BRisusedasaninputofALU,itholdsotheroperandforALU.Inourdesign,BRhas
16bits.
LPM_RAM_DQ
LPM_RAM_DQisaRAMwithseparateinputandoutputports.Itworksasamemory,anditssizeis256×16.Althoughit’snotaninternalregisterofCPU,weneedittosimulateandtesttheperformanceofCPU.
LPM_ROM
LPM_ROMisaROMwithoneaddressinputportandonedataoutputport,anditssizeofdatais32bitswhichcontainscontrolsignalstoexecutemicro-operations.
IV.ALU
ALU(ArithmeticLogicUnit)isacalculationunitwhichaccomplishesbasicarithmeticandlogicoperations.Inourdesign,someoperationsmustbesupportedwhicharelistedasfollows:
Table3ALUOperations
ALUcontrolsignal
Operations
Explanations
3H
ADD
ACC←ACC+BR
4H
SUB
ACC←ACC-BR
6H
AND
ACC←ACCandBR
7H
OR
ACC←ACCorBR
8H
NOT
ACC←notACC
9H
SHIFTR
ACC←ShiftACCtoRight1bit
0AH
SHIFTL
ACC←ShiftACCtoLeft1bit
V.Micro-programmedControlUnit
IntheMicroprogrammedcontrol,themicroprogramconsistsofsomemicroinstructionandthemicroprogramisstoredincontrolmemorythatgeneratesallthecontrolsignalsrequiredtoexecutetheinstructionsetcorrectly.Themicroinstructioncontainssomemicro-operationswhichareexecutedatthesametime.
Figure2showsthekeyelementsofsuchanimplementation.
Thesetofmicroinstructionsisstoredinthecontrolmemory.Thecontroladdressregistercontainstheaddressofthenextmicroinstructionstoberead.Whenamicroinstructionisreadfromthecontrolmemory,itistransferredtoacontrolbufferregister.Theregisterconnectstothecontrollinesemanatingfromthecontrolunit.Thus,readingamicroinstructionfromthecontrolmemoryisthesameasexecutingthatmicroinstruction.Thethirdelementshowninthefigureisasequencingunitthatloadsthecontroladdressregisterandissuesareadcommand.
Figure2ControlUnitMicro-architecture
(I)Totalcontrolsignalsforinstructionsarelistedasfollows:
Table4Controlsignalsforthemicro-operations
BitsinControlMemory
Micro-operation
Meaning
C0~C7
/
BranchAddresses
C8
PC←0
ClearPC
C9
PC←PC+1
IncrementPC
C10
PC←MBR[7..0]
MBR[7..0]toPC
C11
ACC←0
ClearACC
C12--C15
ALUCONTROL
ControloperationsofALU
C16
R
ReaddatafromMemorytoMBR
C17
W
WritedatatoMemory
C18
MAR←MBR[7..0]
MBR[7..0]toMARasaddress
C19
MAR←PC
PCvaluetoMAR
C20
MBR←ACC
ACCvaluetoMBR
C21
IR←MBR[15..8]
MBR[15..8]toIRasopcode
C22
BR←MBR
CopyMBRtoBR
C23
CAR←CAR+1
IncrementCAR
C24
CAR←C0~C7
C7~C0toCAR
C25
CAR←OPCODE+CAR
AddOPtoCAR
C26
CAR←0
ResetCAR
C27--C31
Notuse
-----------
(II)Thecontentsinrom.mifandthecorrespondingmicroprogramsarelistedasfollows:
0:
00810000;R←1,CAR←CAR+1
1:
00A00000;OP←MBR[15..8],CAR←CAR+1
2:
02000000;CAR←CAR+OP
3:
01000014;CAR←14H
4:
01000019;CAR←19H
5:
0100001E;CAR←1EH
6:
01000023;CAR←23H
7:
01000041;CAR←41H
8:
01000028;CAR←28H
9:
0100002D;CAR←2DH
a:
01000032;CAR←32H
b:
01000037;CAR←37H
c:
0100003C;CAR←3CH
d:
01000046;CAR←46H
e:
0100004B;CAR←4H
f:
00000000;
………
14:
00840000;MAR←MBR[7..0],CAR←CAR+1------STORE
15:
00920200;MBR←ACC,PC←PC+1,W←1,CAR←CAR+1
16:
04080000;CAR←0
17:
00000000;
18:
00000000;
19:
00840000;MAR←MBR[7..0],CAR←CAR+1------LOAD
1a:
00810A00;PC←PC+1,R←1,ACC←0,CAR←CAR+1
1b:
00C03000;BR←MBR,ACC←ACC+BR,CAR←CAR+1
1c:
04080000;CAR←0
1d:
00000000;
1e:
00840000;MAR←MBR[7..0],CAR←CAR+1----------ADD
1f:
00810200;PC←PC+1,R←1,CAR←CAR+1
20:
00C03000;BR←MBR,ACC←ACC+BR,CAR←CAR+1
21:
04080000;CAR←0
22:
00000000;
23:
00840000;MAR←MBR[7..0],CAR←CAR+1----------SUB
24:
00810200;PC←PC+1,R←1,CAR←CAR+1
25:
00C04000;BR←MBR,ACC←ACC-BR,CAR←CAR+1
26:
04080000;CAR←0
27:
00000000;
28:
00840000;MAR←MBR[7..0],CAR←CAR+1---------AND
29:
00810200;PC←PC+1,R←1,CAR←CAR+1
2a:
00C06000;BR←MBR,ACC←ACCANDBR,CAR←CAR+1
2b:
04080000;CAR←0
2c:
00000000;
2d:
00840000;MAR←MBR[7..0],CAR←CAR+1---------OR
2e:
00810200;PC←PC+1,R←1,CAR←CAR+1
2f:
00C07000;BR←MBR,ACC←ACCORBR,CAR←CAR+1
30:
04080000;CAR←0
31:
00000000;
32:
00840000;MAR←MBR[7..0],CAR←CAR+1----------NOT
33:
00808200;PC←PC+1,ACC←NOTACC,CAR←CAR+1
34:
04080000;CAR←0
35:
00000000;
36:
00000000;
37:
00840000;MAR←MBR[7..0],CAR←CAR+1----------SHIFTR
38:
08092000;PC←PC+1,ACC←SHIFTACCtoRight1bit,CAR←CAR+1
39:
04080000;CAR←0
3a:
00000000;
3b:
00000000;
3c:
00840000;MAR←MBR[7..0],CAR←CAR+1-----------SHIFTL
3d:
0080A200;PC←PC+1,ACC←SHIFTACCtoLeft1bit,CAR←CAR+1
3e:
04080000;CAR←0
3f:
00000000;
40:
00000000;
41:
00840000;MAR←MBR[7..0],CAR←CAR+1-----------JMPGEZ
42:
00805000;CAR←CAR+1,
43:
04080000;CAR←0
44:
00000000;
45:
00000000;
46:
00840000;MAR←MBR[7..0],CAR←CAR+1------------MPY
47:
00810200;PC←PC+1,R←1,CAR←CAR+1
48:
00C0B000;BR←MBR,ACC←ACC*BR,CAR←CAR+1
49:
04080000;CAR←0
4a:
00000000;
4b:
0100004B;CAR←4BH------------------------------HALT
4c:
00000000;
(III)Thesimulationwaveformsofsomeoperates
1,load,add,store,halt(22+10)
ThecontentsinRAM:
0:
022A;Load2A
1:
032B;ADD2B
2:
012C;Store2C
3:
0C00;Halt
2a:
0016;