VHDL8位CPU设计包含程序.docx

1、VHDL8位CPU设计包含程序Computer Organization and ArchitectureCourse DesignThe Experiment Report OfCPUI . PurposeThe purpose of this project is to design a simple CPU (Central Processing Unit). This CPU has basic instruction set, and we will utilize its instruction set to generate a very simple program to ve

2、rify its performance. For simplicity, we will only consider the relationship among the CPU, registers, memory and instruction set. That is to say we only need consider the following items: Read/Write Registers, Read/Write Memory and Execute the instructions.At least four parts constitute a simple CP

3、U: the control unit, the internal registers, the ALU and instruction set, which are the main aspects of our project design and will be studied.II . Instruction SetSingle-address instruction format is used in our simple CPU design. The instruction word contains two sections: the operation code (opcod

4、e), which defines the function of instructions (addition, subtraction, logic operations, etc.); the address part, in most instructions, the address part contains the memory location of the datum to be operated, we called it direct addressing. In some instructions, the address part is the operand, wh

5、ich is called immediate addressing.For simplicity, the size of memory is 256 16 in the computer. The instruction word has 16 bits. The opcode part has 8 bits and address part has 8 bits. The instruction word format can be expressed in Figure 1:OPCODE15.0ADDRESS7.0Figure 1 the instruction formatThe o

6、pcode of the relevant instructions are listed in Table 1.In Table 1, the notation x represents the contents of the location x in the memory. For example, the instruction word 00000011101110012 (03B916) means that the CPU adds word at location B916 in memory into the accumulator (ACC); the instructio

7、n word 00000101000001112 (050716) means if the sign bit of the ACC (ACC 15) is 0, the CPU will use the address part of the instruction as the address of next instruction, if the sign bit is 1, the CPU will increase the program counter (PC) and use its content as the address of the next instruction.T

8、able 1 List of opcode of the relevant instructionsINSTRUCTIONOPCODECOMMENTSSTORE X01HACCXLOAD X02HXACCADD X03HACC+XACCSUB X04HACC-XACCJMPGZ X05HIF ACC0 THEN XPC ELSE PC+1PCAND X06HACC and XACCOR X07HACC or XACCNOT X08HNot XACCSHIFTR X09HSHIFL ACC to RIGHT 1 bit, Logic ShiftSHIFTL X0AHSHIFT ACC to LE

9、FT 1 bit, Logic ShiftMPY X 0BHACCXACCHALT0CHHALT A PROGRAMA program is designed to test these instructions:Calculate the sum of all integers from 1 to 100.(1), programming with C language:sum=0;temp=100;loop :sum=sum+temp;temp=temp-1;if temp=0 goto loop;end(2), Assume in the RAM_DQ:sum is stored at

10、location A4,temp is stored at location A3,the contents of location A0 is 0,the contents of location A1 is 1,the contents of location A2 is 10010=6416.We can translate the above C language program with the instructions listed in Table 1 into the instruction program as shown in Table 2. Table 2 Exampl

11、e of a program to sum from 1 to 100Program with CProgram withinstructionsContents of RAM_DQ in HEXAddressContentssum=0;LOAD A00002A0STORE A40101A4temp=100LOAD A20202A2STORE A30301A3loop:sum=sum+temp;LOOP:LOAD A40402A4ADD A30503A3STORE A40601A4temp=temp-1;LOAD A30702A3SUB A10804A1STORE A30901A3if tem

12、p0 goto loop;JMPGZ LOOP0A0504end;HALT0B0C000CA00000A10001A20064A3A4III. Internal Registers and MemoryMAR (Memory Address Register) MAR contains the memory location of the word to be read from the memory or written into the memory. Here, READ operation is denoted as the CPU reads from memory, and WRI

13、TE operation is denoted as the CPU writes to memory. In our design, MAR has 8 bits to access one of 256 addresses of the memory.MBR (Memory Buffer Register)MBR contains the value to be stored in memory or the last value read from memory. MBR is connected to the address lines of the system bus. In ou

14、r design, MBR has 16 Bits.PC (Program Counter)PC keeps track of the instructions to be used in the program. In our design, PC has 8 bits.IR (Instruction Register)IR contains the opcode part of an instruction. In our design, IR has 8 bits.BR (Buffer Register)BR is used as an input of ALU, it holds ot

15、her operand for ALU. In our design, BR has16 bits.LPM_RAM_DQLPM_RAM_DQ is a RAM with separate input and output ports. It works as a memory, and its size is 25616. Although its not an internal register of CPU, we need it to simulate and test the performance of CPU.LPM_ROMLPM_ROM is a ROM with one add

16、ress input port and one data output port, and its size of data is 32bits which contains control signals to execute micro-operations.IV.ALUALU (Arithmetic Logic Unit) is a calculation unit which accomplishes basic arithmetic and logic operations. In our design, some operations must be supported which

17、 are listed as follows:Table 3 ALU OperationsALU control signalOperationsExplanations3HADDACCACC+BR4HSUBACCACC- BR6HANDACCACC and BR7HORACCACC or BR8HNOTACCnot ACC9HSHIFTRACCShift ACC to Right 1 bit0AHSHIFTLACCShift ACC to Left 1 bitV. Micro-programmed Control UnitIn the Microprogrammed control, the

18、 microprogram consists of some microinstruction and the microprogram is stored in control memory that generates all the control signals required to execute the instruction set correctly. The microinstruction contains some micro-operations which are executed at the same time.Figure 2 shows the key el

19、ements of such an implementation.The set of microinstructions is stored in the control memory. The control address register contains the address of the next microinstructions to be read. When a microinstruction is read from the control memory, it is transferred to a control buffer register. The regi

20、ster connects to the control lines emanating from the control unit. Thus, reading a microinstruction from the control memory is the same as executing that microinstruction. The third element shown in the figure is a sequencing unit that loads the control address register and issues a read command.Fi

21、gure 2 Control Unit Micro-architecture(I)Total control signals for instructions are listed as follows:Table 4 Control signals for the micro-operationsBits in Control MemoryMicro-operationMeaningC0C7/Branch AddressesC8PC0Clear PCC9PCPC+1Increment PCC10PCMBR7.0MBR7.0 to PCC11ACC0Clear ACCC12-C15ALU CO

22、NTROLControl operations of ALUC16RRead data from Memory to MBRC17WWrite data to Memory C18MARMBR7.0MBR7.0 to MAR as addressC19MARPCPC value to MARC20MBRACCACC value to MBRC21IRMBR15.8MBR15.8 to IR as opcodeC22BRMBRCopy MBR to BRC23CARCAR+1Increment CARC24CARC0C7C7C0 to CAR C25CAROPCODE+CARAdd OP to

23、CARC26CAR0Reset CARC27-C31Not use-(II)The contents in rom.mif and the corresponding microprograms are listed as follows: 0 : 00810000; R1, CARCAR+1 1 : 00A00000; OPMBR15.8,CARCAR+1 2 : 02000000; CARCAR+OP 3 : 01000014; CAR14H 4 : 01000019; CAR19H 5 : 0100001E; CAR1EH 6 : 01000023; CAR23H 7 : 0100004

24、1; CAR41H 8 : 01000028; CAR28H 9 : 0100002D; CAR2DH a : 01000032; CAR32H b : 01000037; CAR37H c : 0100003C; CAR3CH d : 01000046; CAR46H e : 0100004B; CAR4H f : 00000000; 14 : 00840000; MARMBR7.0, CARCAR+1 -STORE 15 : 00920200; MBRACC, PCPC+1,W1,CARCAR+1 16 : 04080000; CAR0 17 : 00000000; 18 : 000000

25、00; 19 : 00840000; MARMBR7.0, CARCAR+1 -LOAD 1a : 00810A00; PCPC+1,R1,ACC0,CARCAR+1 1b : 00C03000; BRMBR,ACCACC+BR, CARCAR+1 1c : 04080000; CAR0 1d : 00000000; 1e : 00840000; MARMBR7.0, CARCAR+1 -ADD 1f : 00810200; PCPC+1,R1,CARCAR+1 20 : 00C03000; BRMBR,ACCACC+BR, CARCAR+1 21 : 04080000; CAR0 22 :

26、00000000; 23 : 00840000; MARMBR7.0, CARCAR+1 -SUB 24 : 00810200; PCPC+1,R1,CARCAR+1 25 : 00C04000; BRMBR,ACCACC-BR, CARCAR+1 26 : 04080000; CAR0 27 : 00000000; 28 : 00840000; MARMBR7.0, CARCAR+1 -AND 29 : 00810200; PCPC+1,R1,CARCAR+1 2a : 00C06000; BRMBR,ACCACC AND BR,CARCAR+1 2b : 04080000; CAR0 2c

27、 : 00000000; 2d : 00840000; MARMBR7.0, CARCAR+1 -OR 2e : 00810200; PCPC+1,R1,CARCAR+1 2f : 00C07000; BRMBR,ACCACC OR BR, CARCAR+1 30 : 04080000; CAR0 31 : 00000000; 32 : 00840000; MARMBR7.0, CARCAR+1 -NOT 33 : 00808200; PCPC+1, ACCNOT ACC,CARCAR+1 34 : 04080000; CAR0 35 : 00000000; 36 : 00000000; 37

28、 : 00840000; MARMBR7.0, CARCAR+1 -SHIFTR 38 : 08092000; PCPC+1, ACCSHIFT ACC to Right 1 bit,CARCAR+1 39 : 04080000; CAR0 3a : 00000000; 3b : 00000000; 3c : 00840000; MARMBR7.0, CARCAR+1 -SHIFTL 3d : 0080A200; PCPC+1, ACCSHIFT ACC to Left 1 bit,CARCAR+1 3e : 04080000; CAR0 3f : 00000000; 40 : 0000000

29、0; 41 : 00840000; MARMBR7.0, CARCAR+1 -JMPGEZ 42 : 00805000; CARCAR+1, 43 : 04080000; CAR0 44 : 00000000; 45 : 00000000; 46 : 00840000; MARMBR7.0, CARCAR+1 -MPY 47 : 00810200; PCPC+1,R1,CARCAR+1 48 : 00C0B000; BRMBR,ACCACC*BR, CARCAR+1 49 : 04080000; CAR0 4a : 00000000; 4b : 0100004B; CAR4BH -HALT 4c : 00000000;(III)The simulation waveforms of some operates1, load, add, store, halt (22+10)The contents in RAM: 0 : 022A; Load 2A 1 : 032B; ADD 2B 2 : 012C; Store 2C 3 : 0C00; Halt2a : 0016;