DRAM1.docx

DRAM1.docx

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DRAM1

Dynamicrandom-accessmemory

Dynamicrandom-accessmemory （DRAM）isatypeof random-accessmemory thatstoreseach bit ofdatainaseparate capacitorwithinan integratedcircuit.Thecapacitorcanbeeitherchargedordischarged;thesetwostatesaretakentorepresentthetwovaluesofabit,conventionallycalled0and1.Sincecapacitorsleakcharge,theinformationeventuallyfadesunlessthecapacitorchargeis refreshed periodically.Becauseofthisrefreshrequirement,itisa dynamic memoryasopposedto SRAM andother static memory.

Themainmemory（the"RAM"）inpersonalcomputersisDynamicRAM（DRAM）,asisthe"RAM"ofhomegameconsoles（PlayStation,Xbox360 and Wii）, laptop, notebook and workstation computers.

TheadvantageofDRAMisitsstructuralsimplicity:

onlyonetransistorandacapacitorarerequiredperbit,comparedtosixtransistorsinSRAM.ThisallowsDRAMtoreachveryhigh densities.Unlike flashmemory,DRAMis volatilememory （cf. non-volatilememory）,sinceitlosesitsdataquicklywhenpowerisremoved.Thetransistorsandcapacitorsusedareextremelysmall;hundredsofbillionscanfitonasinglememorychip.

History

The cryptanalytic machinecode-named "Aquarius" usedat BletchleyPark during WorldWarII incorporatedahard-wireddynamicmemory.Papertapewasreadandthecharactersonit"wererememberedinadynamicstore....Thestoreusedalargebankofcapacitors,whichwereeitherchargedornot,achargedcapacitorrepresentingcross

（1）andanunchargedcapacitordot（0）.Sincethechargegraduallyleakedaway,aperiodicpulsewasappliedtotopupthosestillcharged（hencetheterm'dynamic'）".[1]

In1964,ArnoldFarberandEugeneSchlig,workingforIBM,createdamemorycellthatwashardwired.Itusedatransistorgateandtunneldiodelatch.Theyreplacedthelatchwithtwotransistorsandtworesistors.ThisconfigurationbecameknownastheFarber-Schligcell.In1965,BenjaminAgustaandhisteamatIBMmanagedtocreatea16-bitsiliconmemorychipbasedontheFarber-Schligcell,whichconsistedof80transistors,64resistors,andfourdiodes.In1966,DRAMwasinventedbyDr. RobertDennard atthe IBM ThomasJ.WatsonResearchCenter.HewasawardedU.S.patentnumber 3,387,286 in1968.Capacitorshadbeenusedforearliermemoryschemessuchasthedrumofthe Atanasoff–BerryComputer,the Williamstube andthe Selectrontube.

SchematicdrawingoforiginaldesignsofDRAMpatentedin1968.

ThefirstDRAMwithmultiplexedrowandcolumnaddresslineswasthe Mostek MK4096（4096x1）designedby RobertProebsting andintroducedin1973.Thisaddressingscheme,aradicaladvance,enabledittofitintopackageswithfewerpins,acostadvantagethatwouldgrowwitheveryjumpinmemorysize.TheMK4096provedtobeaveryrobustdesignforcustomerapplications.Atthe16Kdensity,thecostadvantageincreased,andtheMostekMK411616KDRAM,introducedin1976,achievedgreaterthan75%worldwideDRAMmarketshare.However,asdensityincreasedto64Kintheearly80s,MostekwasovertakenbyJapaneseDRAMmanufacturerssellinghigherqualityDRAMsusingthesamemultiplexingschemeatbelow-costprices.

Operationprinciple

DRAMisusuallyarrangedinasquarearrayofonecapacitorandtransistorperdatabitstoragecell.Theillustrationstotherightshowasimpleexamplewithonly4by4cells（ModernDRAMmatrixaremanythousandsofcellsinheightandwidth）.

PrincipleofoperationofDRAMread,forsimple4by4array.

PrincipleofoperationofDRAMwrite,forsimple4by4array.

Toreadabitfromacolumn,thefollowingoperationstakeplace:

1.Thesenseamplifierisdisconnected,thenthebitlinesareprechargedtoexactlyequalvoltagesthatarein-betweenhighandlowlogiclevels.Thebitlinesarephysicallysymmetricaltokeepthecapacitanceasequalandthereforethevoltagesasequalaspossible.

2.Theprechargecircuitisswitchedoff.Becausethebitlinesarerelativelylong,theyhaveenoughcapacitance tomaintainthepre-chargedvoltageforabrieftime.Thisisanexampleof dynamiclogic.

3.Thedesiredrow'swordlineisthendrivenhightoconnectacell'sstoragecapacitortoitsbitline.Thiscausesthetransistortoconduct,transferring charge betweenthestoragecellandtheconnectedbitline.Ifthestoragecellcapacitorisdischarged,itwillgreatlydecreasethevoltageonthebit-lineastheprechargeistransferredtothestoragecapacitor.Ifthestoragecellischarged,thebit-linevoltagedecreasesonlyslightly;thisbecauseeveryeffortismadetokeepthecapacitanceofthestoragecellshighandthecapacitanceofthebitlineslow.

4.Thesenseamplifierisswitchedon.Thepositivefeedbacktakesoverandamplifiesthesmallvoltagedifferencebetweenbit-linesuntilonebitlineisfullyatthelowestvoltageandtheotherisatthemaximumhighvoltage.Oncethishashappened,therowis"open"（thedesiredcelldataisavailable）.

5.Allcolumnsaresensedinsimultaneouslyandtheresultsampledintothedatalatch.AprovidedColumnaddressthenselectswhichlatchbittoconnecttotheexternalcircuit.Manyreadscanbeperformedquicklywithoutdelaysensefortheopenrow,alldatahasalreadybeensensedandlatched.

6.Whilereadingallcolumnsproceeds（thenormalanddesirablemethodbecauseitmostquicklyprovidesdata）,currentisflowingbackupthebitlinesfromthesenseamplifierstothestoragecells.Thisreinforces（i.e."refreshes"）thechargeinthestoragecellbyincreasingthevoltageinthestoragecapacitorifitwaschargedtobeginwith,orbykeepingitdischargedifitwasempty.Notethatduetothelengthofthebitlinescreatingafairlylongpropagationdelayforthechargetobetransferred,thistakessignificanttimebeyondtheendofsenseamplification,andthusoverlapswithoneormorecolumnreads.

7.Whendonewiththereadingallthecolumnsinthecurrentrow,thewordlineisswitchedofftodisconnectthecellstoragecapacitors（therowis"closed"）,thesenseamplifierisswitchedoff,andthebitlinesareprechargedagain.

Towritetomemory,therowisopenedandagivencolumn'ssenseamplifieristemporarilyforcedtothedesiredhighorlowvoltagestate,thusitdrivesthebitlinetochargeordischargethecellstoragecapacitortothedesiredvalue.Duetopositivefeedback,theamplifierwillthenholditstableevenaftertheforcingisremoved.Duringawritetoaparticularcell,allthecolumnsinarowaresensedsimultaneouslyjustasinreading,asinglecolumn'scellstoragecapacitorchargeischanged,andthentheentirerowiswrittenbackin,asillustratedinthefiguretotheright.

Typically,manufacturersspecifythateachrowmustbehaveitsstoragecellcapacitorsrefreshedevery64 msorless,asdefinedbythe JEDEC （FoundationfordevelopingSemiconductorStandards）standard. Refreshlogic isprovidedinaDRAMcontrollerwhichautomatestheperiodicrefresh,thatisnosoftwareorotherhardwarehastoperformit.Thismakesthecontroller'slogiccircuitmorecomplicated,butthisdrawbackisoutweighedbythefactthatDRAMismuchcheaperperstoragecellandbecauseeachstoragecellisverysimple,DRAMhasmuchgreatercapacitypergeographicareathanSRAM.

Somesystemsrefresheveryrowinaburstofactivityinvolvingallrowsevery64 ms.Othersystemsrefreshonerowatatimestaggeredthroughoutthe64msinterval.Forexample,asystemwith213 = 8192rowswouldrequireastaggered refreshrate ofonerowevery7.8 µswhichis64 msdividedby8192rows.Afewreal-timesystemsrefreshaportionofmemoryatatimedeterminedbyanexternaltimerfunctionthatgovernstheoperationoftherestofasystem,suchasthe verticalblankinginterval thatoccursevery10–20 msinvideoequipment.Allmethodsrequiresomesortofcountertokeeptrackofwhichrowisthenexttoberefreshed.MostDRAMchipsincludethatcounter.Oldertypesrequireexternalrefreshlogictoholdthecounter.（Undersomeconditions,mostofthedatainDRAMcanberecoveredeveniftheDRAMhasnotbeenrefreshedforseveralminutes.

Memorytiming

TherearemanynumbersrequiredtodescribethetimingofDRAMoperation.HerearesomeexamplesfortwotiminggradesofasynchronousDRAM,fromadatasheetpublishedin1998:

[3]

"50 ns"

"60 ns"

Description

tRC

84 ns

104 ns

Randomreadorwritecycletime（fromonefull/RAScycletoanother）

tRAC

50 ns

60 ns

Accesstime:

/RASlowtovaliddataout

tRCD

11 ns

14 ns

/RASlowto/CASlowtime

tRAS

50 ns

60 ns

/RASpulsewidth（minimum/RASlowtime）

tRP

30 ns

40 ns

/RASprechargetime（minimum/RAShightime）

tPC

20 ns

25 ns

Page-modereadorwritecycletime（/CASto/CAS）

tAA

25 ns

30 ns

Accesstime:

Columnaddressvalidtovaliddataout（includesaddress setuptime before/CASlow）

tCAC

13 ns

15 ns

Accesstime:

/CASlowtovaliddataout

tCAS

8 ns

10 ns

/CASlowpulsewidthminimum

Thus,thegenerallyquotednumberisthe/RASaccesstime.ThisisthetimetoreadarandombitfromaprechargedDRAMarray.Thetimetoreadadditionalbitsfromanopenpageismuchless.

WhensuchaRAMisaccessedbyclockedlogic,thetimesaregenerallyroundeduptothenearestclockcycle.Forexample,whenaccessedbya100 MHzstatemachine（i.e.a10 nsclock）,the50 nsDRAMcanperformthefirstreadinfiveclockcycles,andadditionalreadswithinthesamepageeverytwoclockcycles.Thiswasgenerallydescribedas "5‐2‐2‐2" timing,asburstsoffourreadswithinapagewerecommon.

Whendescribingsynchronousmemory,timingisdescribedbyclockcyclecountsseparatedbyhyphens.Thesenumbersrepresent tCL‐tRCD‐tRP‐tRAS inmultiplesoftheDRAMclockcycletime.Notethatth