DSP281xEvh.docx

DSP281xEvh.docx

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DSP281xEvh

//FILE:

DSP28_Ev.h

//TITLE:

DSP28DeviceEventManagerRegisterDefinitions.

#ifndefDSP28_EV_H

#defineDSP28_EV_H

/*F2810/12EventManager（EV）GPTimerRegisters*/

/*OverallTimerControlRegister*/

structGPTCONA_BITS{

Uint16T1PIN:

2;//1:

0PolarityofGPtimer1compare

Uint16T2PIN:

2;//3:

2PolarityofGPtimer2compare

Uint16rsvd1:

2;//5:

4reserved

Uint16TCOMPOE:

1;//6Compareoutputenable

Uint16T1TOADC:

2;//8:

7StartADCwithtimer1event

Uint16T2TOADC:

2;//10:

9StartADCwithtimer2event

Uint16rsvd2:

2;//12:

11reserved

Uint16T1STAT:

1;//13GPTimer1status（readonly）

Uint16T2STAT:

1;//14GPTimer2status（readonly）

Uint16rsvd:

1;//15reserved

};

/*Allowaccesstothebitfieldsorentireregister*/

unionGPTCONA_REG{

Uint16all;

structGPTCONA_BITSbit;

};

structGPTCONB_BITS{

Uint16T3PIN:

2;//1:

0PolarityofGPtimer3compare

Uint16T4PIN:

2;//3:

2PolarityofGPtimer4compare

Uint16T1CMPOE:

1;//4Timer1compareoutput

Uint16T2CMPOE:

1;//5Timer2compareoutput

Uint16TCOMPOE:

1;//6Compareoutputenable

Uint16T3TOADC:

2;//8:

7StartADCwithtimer3event

Uint16T4TOADC:

2;//10:

9StartADCwithtimer4event

Uint16T1CTRIP:

1;//11Timer1tripenable

Uint16T2CTRIP:

1;//12Timer2tripenable

Uint16T3STAT:

1;//13GPTimer3status（readonly）

Uint16T4STAT:

1;//14GPTimer4status（readonly）

Uint16rsvd:

1;//15reserved

};

/*Allowaccesstothebitfieldsorentireregister*/

unionGPTCONB_REG{

Uint16all;

structGPTCONB_BITSbit;

};

/*TimerControlRegisterbitdefintions*/

structTCONA_BITS{

Uint16SET1PR:

1;//0Periodregisterselect

Uint16TECMPR:

1;//1Timercompareenable

Uint16TCLD10:

2;//3:

2Timercopareregisterreload

Uint16TCLKS10:

2;//5:

4Clocksourceselect

Uint16TENABLE:

1;//6Timerenable

Uint16T2SWT1:

1;//7StartGPtimer2withGPtimer1'senable

Uint16TPS:

3;//10:

8Inputclockprescaler

Uint16TMODE:

2;//12:

11Countmodeselection

Uint16rsvd:

1;//13reserved

Uint16FREE:

1;//14Freeemulationcontrol

Uint16SOFT:

1;//15Softemulationcontrol

};

/*Allowaccesstothebitfieldsorentireregister*/

unionTCONA_REG{

Uint16all;

structTCONA_BITSbit;

};

structTCONB_BITS{

Uint16SET3PR:

1;//0Periodregisterselect

Uint16TECMPR:

1;//1Timercompareenable

Uint16TCLD10:

2;//3:

2Timercopareregisterreload

Uint16TCLKS10:

2;//5:

4Clocksourceselect

Uint16TENABLE:

1;//6Timerenable

Uint16T4SWT3:

1;//7StartGPtimer2withGPtimer1'senable

Uint16TPS:

3;//10:

8Inputclockprescaler

Uint16TMODE:

2;//12:

11Countmodeselection

Uint16rsvd:

1;//13reserved

Uint16FREE:

1;//14Freeemulationcontrol

Uint16SOFT:

1;//15Softemulationcontrol

};

/*Allowaccesstothebitfieldsorentireregister*/

unionTCONB_REG{

Uint16all;

structTCONB_BITSbit;

};

structEXTCONA_BITS{

Uint16INDCOE:

1;//0Independantcompareoutput

Uint16QEPIQEL:

1;//1QEP/CAP3IndexQualMode

Uint16QEPIE:

1;//2QEPindexenable

Uint16EVSOCE:

1;//3Evstartofconversionoutputenable

Uint16rsvd:

12;//15:

4reserved

};

/*Allowaccesstothebitfieldsorentireregister*/

unionEXTCONA_REG{

Uint16all;

structEXTCONA_BITSbit;

};

structEXTCONB_BITS{

Uint16INDCOE:

1;//0Independantcompareoutput

Uint16QEPIQEL:

1;//1QEP/CAP3IndexQualMode

Uint16QEPIE:

1;//2QEPindexenable

Uint16EVSOCE:

1;//3Evstartofconversionoutputenable

Uint16rsvd:

12;//15:

4reserved

};

/*Allowaccesstothebitfieldsorentireregister*/

unionEXTCONB_REG{

Uint16all;

structEXTCONA_BITSbit;

};

/*CompareControlRegister*/

structCOMCONA_BITS{

Uint16rsvd:

8;//7:

0reserved

Uint16PDPINTASTATUS:

1;//8CurrentstatusofthePDPINTApin

Uint16FCOMPOE:

1;//9Compareoutputenable

Uint16ACTRLD:

2;//11:

10Actioncontrolregisterreload

Uint16SVENABLE:

1;//12SpacevectorPWMModeenable

Uint16CLD:

2;//14:

13Compareregisterreloadcondition

Uint16CENABLE:

1;//15Compareenable

};

/*Allowaccesstothebitfieldsorentireregister*/

unionCOMCONA_REG{

Uint16all;

structCOMCONA_BITSbit;

};

structCOMCONB_BITS{

Uint16rsvd:

8;//7:

0reserved

Uint16PDPINTBSTATUS:

1;//8CurrentstatusofthePDPINTBpin

Uint16FCOMPOE:

1;//9Compareoutputenable

Uint16ACTRLD:

2;//11:

10Actioncontrolregisterreload

Uint16SVENABLE:

1;//12SpacevectorPWMModeenable

Uint16CLD:

2;//14:

13Compareregisterreloadcondition

Uint16CENABLE:

1;//15Compareenable

};

/*Allowaccesstothebitfieldsorentireregister*/

unionCOMCONB_REG{

Uint16all;

structCOMCONB_BITSbit;

};

/*CompareActionControlRegisterbitdefinitions*/

structACTRA_BITS{

Uint16CMP1ACT:

2;//1:

0Actiononcompareoutputpin1CMP1

Uint16CMP2ACT:

2;//3:

2Actiononcompareoutputpin2CMP