AT89S51英文手册.pdf

AT89S51英文手册.pdf

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FeaturesCompatiblewithMCS-51Products4KBytesofIn-SystemProgrammable（ISP）FlashMemoryEndurance:

10,000Write/EraseCycles4.0Vto5.5VOperatingRangeFullyStaticOperation:

0Hzto33MHzThree-levelProgramMemoryLock128x8-bitInternalRAM32ProgrammableI/OLinesTwo16-bitTimer/CountersSixInterruptSourcesFullDuplexUARTSerialChannelLow-powerIdleandPower-downModesInterruptRecoveryfromPower-downModeWatchdogTimerDualDataPointerPower-offFlagFastProgrammingTimeFlexibleISPProgramming（ByteandPageMode）Green（Pb/Halide-free）PackagingOption1.DescriptionTheAT89S51isalow-power,high-performanceCMOS8-bitmicrocontrollerwith4KbytesofIn-SystemProgrammableFlashmemory.ThedeviceismanufacturedusingAtmelshigh-densitynonvolatilememorytechnologyandiscompatiblewiththeindus-try-standard80C51instructionsetandpinout.Theon-chipFlashallowstheprogrammemorytobereprogrammedin-systemorbyaconventionalnonvolatilememorypro-grammer.Bycombiningaversatile8-bitCPUwithIn-SystemProgrammableFlashonamonolithicchip,theAtmelAT89S51isapowerfulmicrocontrollerwhichprovidesahighly-flexibleandcost-effectivesolutiontomanyembeddedcontrolapplications.TheAT89S51providesthefollowingstandardfeatures:

4KbytesofFlash,128bytesofRAM,32I/Olines,Watchdogtimer,twodatapointers,two16-bittimer/counters,afive-vectortwo-levelinterruptarchitecture,afullduplexserialport,on-chiposcillator,andclockcircuitry.Inaddition,theAT89S51isdesignedwithstaticlogicforoperationdowntozerofrequencyandsupportstwosoftwareselectablepowersavingmodes.TheIdleModestopstheCPUwhileallowingtheRAM,timer/counters,serialport,andinterruptsystemtocontinuefunctioning.ThePower-downmodesavestheRAMcon-tentsbutfreezestheoscillator,disablingallotherchipfunctionsuntilthenextexternalinterruptorhardwarereset.8-bitMicrocontrollerwith4KBytesIn-SystemProgrammableFlashAT89S512487DMICRO6/0822487DMICRO6/08AT89S512.PinConfigurations2.140-leadPDIP2.244-leadTQFP12345678910111213141516171819204039383736353433323130292827262524232221P1.0P1.1P1.2P1.3P1.4（MOSI）P1.5（MISO）P1.6（SCK）P1.7RST（RXD）P3.0（TXD）P3.1（INT0）P3.2（INT1）P3.3（T0）P3.4（T1）P3.5（WR）P3.6（RD）P3.7XTAL2XTAL1GNDVCCP0.0（AD0）P0.1（AD1）P0.2（AD2）P0.3（AD3）P0.4（AD4）P0.5（AD5）P0.6（AD6）P0.7（AD7）EA/VPPALE/PROGPSENP2.7（A15）P2.6（A14）P2.5（A13）P2.4（A12）P2.3（A11）P2.2（A10）P2.1（A9）P2.0（A8）1234567891011333231302928272625242344434241403938373635341213141516171819202122（MOSI）P1.5（MISO）P1.6（SCK）P1.7RST（RXD）P3.0NC（TXD）P3.1（INT0）P3.2（INT1）P3.3（T0）P3.4（T1）P3.5P0.4（AD4）P0.5（AD5）P0.6（AD6）P0.7（AD7）EA/VPPNCALE/PROGPSENP2.7（A15）P2.6（A14）P2.5（A13）P1.4P1.3P1.2P1.1P1.0NCVCCP0.0（AD0）P0.1（AD1）P0.2（AD2）P0.3（AD3）（WR）P3.6（RD）P3.7XTAL2XTAL1GNDGND（A8）P2.0（A9）P2.1（A10）P2.2（A11）P2.3（A12）P2.42.344-leadPLCC78910111213141516173938373635343332313029（MOSI）P1.5（MISO）P1.6（SCK）P1.7RST（RXD）P3.0NC（TXD）P3.1（INT0）P3.2（INT1）P3.3（T0）P3.4（T1）P3.5P0.4（AD4）P0.5（AD5）P0.6（AD6）P0.7（AD7）EA/VPPNCALE/PROGPSENP2.7（A15）P2.6（A14）P2.5（A13）65432144434241401819202122232425262728（WR）P3.6（RD）P3.7XTAL2XTAL1GNDNC（A8）P2.0（A9）P2.1（A10）P2.2（A11）P2.3（A12）P2.4P1.4P1.3P1.2P1.1P1.0NCVCCP0.0（AD0）P0.1（AD1）P0.2（AD2）P0.3（AD3）32487DMICRO6/08AT89S513.BlockDiagramPORT2DRIVERSPORT2LATCHP2.0-P2.7FLASHPORT0LATCHRAMPROGRAMADDRESSREGISTERBUFFERPCINCREMENTERPROGRAMCOUNTERDUALDPTRINSTRUCTIONREGISTERBREGISTERINTERRUPT,SERIALPORT,ANDTIMERBLOCKSSTACKPOINTERACCTMP2TMP1ALUPSWTIMINGANDCONTROLPORT1DRIVERSP1.0-P1.7PORT3LATCHPORT3DRIVERSP3.0-P3.7OSCGNDVCCPSENALE/PROGEA/VPPRSTRAMADDR.REGISTERPORT0DRIVERSP0.0-P0.7PORT1LATCHWATCHDOGISPPORTPROGRAMLOGIC42487DMICRO6/08AT89S514.PinDescription4.1VCCSupplyvoltage.4.2GNDGround.4.3Port0Port0isan8-bitopendrainbi-directionalI/Oport.Asanoutputport,eachpincansinkeightTTLinputs.When1sarewrittentoport0pins,thepinscanbeusedashigh-impedanceinputs.Port0canalsobeconfiguredtobethemultiplexedlow-orderaddress/databusduringaccessestoexternalprogramanddatamemory.Inthismode,P0hasinternalpull-ups.Port0alsoreceivesthecodebytesduringFlashprogrammingandoutputsthecodebytesdur-ingprogramverification.Externalpull-upsarerequiredduringprogramverification.4.4Port1Port1isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort1outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort1pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,Port1pinsthatareexternallybeingpulledlowwillsourcecurrent（IIL）becauseoftheinternalpull-ups.Port1alsoreceivesthelow-orderaddressbytesduringFlashprogrammingandverification.4.5Port2Port2isan8-bitbi-directionalI/Oportwithinternalpull-ups.ThePort2outputbufferscansink/sourcefourTTLinputs.When1sarewrittentoPort2pins,theyarepulledhighbytheinter-nalpull-upsandcanbeusedasinputs.Asinputs,P