数电答案.docx
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数电答案
习题10
10-1试用VHDL描述一个一位全加器电路。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
entitymy_adderis
port
(
a,b,cin:
inbit;
cout,sum:
outbit
);
endmy_adder;
architecturebehaveofmy_adderis
begin
sum<=axorbxorcin;
cout<=((axorb)andcin)or(aandb);
endbehave;
10-2试编写两个四位二进制相减的VHDL程序。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymy_sub4is
port
(
a:
instd_logic_vector(3downto0);
b:
instd_logic_vector(3downto0);
ci:
instd_logic;
co:
outstd_logic;
result:
outstd_logic_vector(3downto0)
);
endmy_sub4;
architecturebehaveofmy_sub4is
signals:
std_logic_vector(4downto0);
begin
s<=('0'&a)+('0'&b)+("0000"&ci);
result<=s(3downto0);
co<=s(4);
endbehave;
10-3试用VHDL描述一个3-8译码器。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
entitymy_3to8decoderis
port
(
sel:
instd_logic_vector(2downto0);
adr:
outstd_logic_vector(7downto0)
);
endmy_3to8decoder;
architecturebehaveofmy_3to8decoderis
begin
process(sel)
begin
caseselis
when"000"=>adr<="11111110";
when"001"=>adr<="11111101";
when"010"=>adr<="11111011";
when"011"=>adr<="11110111";
when"100"=>adr<="11101111";
when"101"=>adr<="11011111";
when"110"=>adr<="10111111";
when"111"=>adr<="01111111";
whenothers=>adr<=null;
endcase;
endprocess;
endbehave;
mengskyx@
10-4试用VHDL描述一个8421BCD优先编码器。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
entityencoder83is
port(d:
instd_logic_vector(9downto0);
y:
outstd_logic_vector(3downto0));
endencoder83;
architecturearcofencoder83is
begin
process(d)
begin
ifd(9)='0'then
y<="1001";
elsifd(8)='0'then
y<="1000";
elsifd(7)='0'then
y<="0111";
elsifd(6)='0'then
y<="0110";
elsifd(5)='0'then
y<="0101";
elsifd(4)='0'then
y<="0100";
elsifd(3)='0'then
y<="0011";
elsifd
(2)='0'then
y<="0010";
elsifd
(1)='0'then
y<="0001";
else
y<="0000";
endif;
endprocess;
endarc;
10-5试用if语句描述一个4选1数据选择器。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
entitymy_mux4_1is
port(d:
instd_logic_vector(3downto0);
s:
instd_logic_vector(1downto0);
y:
outstd_logic
);
endmy_mux4_1;
architecturebehaviorofmy_mux4_1is
begin
process(s,d)
variablemuxval:
std_logic;
begin
muxval:
='0';
ifs="00"then
muxval:
=d(0);
elsifs="01"then
muxval:
=d
(1);
elsifs="10"then
muxval:
=d
(2);
elsifs="11"then
muxval:
=d(3);
elsenull;
endif;
y<=muxval;
endprocess;
endbehavior;
10-6用VHDL描述时序电路时,时钟和复位信号的描述有哪几种方法?
它们各有什么特点?
解:
时钟信号的描述有两种,边沿触发和电平触发,针对不同的器件选择不同的触发方式。
复位信号的描述也有两种,同步复位和异步复位,故名思意,就是复位信号是否受时钟信号的控制,在描述时,异步复位电路的复位信号要放在process的敏感列表中。
10-7用VHDL描述任意模值二进制计数器和任意模值十进制计数器有何区别?
解:
因为位权不同,二进制计数器与十进制计数器的主要区别是计数的输出设置不同
10-8分频器和计数器有何区别?
用VHDL描述分频器时应注意什么问题?
解:
分频器的时钟脉冲CP一定是周期信号,则输出信号也是周期性,输出信号的周期是输入信号周期的M倍,反过来输出信号的频率是输入信号频率的M分之一。
计数器的时钟脉冲CP不一定是周期信号,可以是随机脉冲,称为计数脉冲,则输出信号也不一定是周期性。
计数器工作目的是纪录计数脉冲个数(递加或递减)以及产生溢出(进位或借位)信号。
描述分频器时应注意分频后波形的占空比的设置。
10-9试用VHDL描述一个具有异步复位、同步置数使能的8位二进制加/减法计数器。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymy_8counteris
port
(
clk:
instd_logic;
reset:
instd_logic;
enable:
instd_logic;
updown:
instd_logic;
q:
outstd_logic_vector(7downto0)
);
endmy_8counter;
architecturertlofmy_8counteris
signaldirection:
integer;
begin
process(updown)
begin
--Determinetheincrement/decrementofthecounter
if(updown='1')then
direction<=1;
else
direction<=-1;
endif;
endprocess;
process(clk)
variablecnt:
std_logic_vector(7downto0);
begin
--Synchronouslyupdatecounter
if(rising_edge(clk))then
ifreset='1'then
--Resetthecounterto0
cnt:
=(others=>'0');
elsifenable='1'then
--Increment/decrementthecounter
cnt:
=cnt+direction;
endif;
endif;
--Outputthecurrentcount
q<=cnt;
endprocess;
endrtl;
10-10试用VHDL设计一个M=100的二进制加法计数器。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymy_100counteris
port
(
clk:
instd_logic;
reset:
instd_logic;
enable:
instd_logic;
q:
outstd_logic_vector(7downto0);
oc:
outstd_logic
);
endmy_100counter;
architecturertlofmy_100counteris
signalcnt:
std_logic_vector(7downto0);
begin
process(clk)
begin
--Synchronouslyupdatecounter
if(rising_edge(clk))then
ifreset='1'then
--Resetthecounterto0
cnt<=(others=>'0');
elsifenable='1'then
cnt<=cnt+1;
endif;
endif;
endprocess;
process(cnt)
begin
ifcnt=99then
oc<='1';
else
oc<='0';
endif;
endprocess;
--Outputthecurrentcount
q<=cnt;
endrtl;
10-11试用VHDL设计一个M=78的十进制加法计数器。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymy_78counteris
port
(
clk:
instd_logic;
reset:
instd_logic;
enable:
instd_logic;
ql,qh:
outstd_logic_vector(3downto0);
oc:
outstd_logic
);
endmy_78counter;
architecturertlofmy_78counteris
signalcntl,cnth:
std_logic_vector(3downto0);
begin
process(reset,clk)
begin
ifreset='0'then
cntl<="0000";
cnth<="0000";
elsifclk'eventandclk='1'then
ifenable='1'then
if(cntl=7andcnth=7)then
cntl<="0000";
cnth<="0000";
elsifcntl=9then
cntl<="0000";
cnth<=cnth+1;
else
cntl<=cntl+1;
endif;
endif;
endif;
endprocess;
process(cntl,cnth)
begin
if(cntl=7andcnth=7)then
oc<='1';
else
oc<='0';
endif;
endprocess;
--Outputthecurrentcount
ql<=cntl;
qh<=cnth;
endrtl;
10-12试用VHDL设计一个M=56的十进制减法计数器
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymy_56counteris
port
(
clk:
instd_logic;
reset:
instd_logic;
enable:
instd_logic;
ql,qh:
outstd_logic_vector(3downto0);
oc:
outstd_logic
);
endmy_56counter;
architecturertlofmy_56counteris
signalcntl,cnth:
std_logic_vector(3downto0);
begin
process(reset,clk)
begin
ifreset='0'then
cntl<="0000";
cnth<="0000";
elsifclk'eventandclk='1'then
ifenable='1'then
if(cntl=5andcnth=5)then
cntl<="0000";
cnth<="0000";
elsifcntl=9then
cntl<="0000";
cnth<=cnth+1;
else
cntl<=cntl+1;
endif;
endif;
endif;
endprocess;
process(cntl,cnth)
begin
if(cntl=5andcnth=5)then
oc<='1';
else
oc<='0';
endif;
endprocess;
--Outputthecurrentcount
ql<=cntl;
qh<=cnth;
endrtl;
10-13试用VHDL设计一个分频电路,要求将4MHz输入信号变为1Hz输出。
解:
程序设计如下:
分频系数:
4000000,计数器从22位全0变为1111010000100011111111时,最高位输出1Hz的脉冲。
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymy_4mis
port
(
clk:
instd_logic;
clkout:
outstd_logic
);
endmy_4m;
architecturertlofmy_78counteris
signalcnt:
std_logic_vector(21downto0);
begin
process
begin
waituntilclk'eventandclk='1';
if(cnt<3999999)then
cnt<=cnt+1;
clkout<='0';
else
cnt<=(others=>'0');
clkout<='1';
endif;
endprocess;
endrtl;
10-14试用VHDL设计一个16位串行输入→并行输出移位寄存器。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityreg16_1is
port
(
clk,ldn,clrn:
inbit;
dsr:
instd_logic;
d:
ininstd_logic_vector(15downto0);
q:
outinstd_logic_vector(15downto0)
);
endreg16_1;
architecturea1ofreg16_1IS
signalsreg16:
instd_logic_vector(15downto0);
begin
process(clrn,clk,ldn,d)
begin
ifclrn='0'then
sreg16<="00000000";
else
ifclk'eventandclk='1'then
ifldn='0'then
sreg8<=d;
else
sreg16(14downto0)<=sreg16(15downto1);
sreg16(15)<=dsr;
endif;
endif;
endif;
q<=sreg16;
endprocess;
enda1
10-15试用VHDL设计一个11010序列码发生器,循环产生11010序列。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
entitymy_serialis
port(
clk:
instd_logic;
z:
outstd_logic
);
endmy_serial;
architecturertlofmy_serialis
typestate_typeis(s0,s1,s2,s3,s4);
signalcurrent_state,next_state:
state_type;
begin
synch:
process
begin
waituntilclk'eventandclk='1';
current_state<=next_state;
endprocess;
state_trans:
process(current_state)
begin
casecurrent_stateis
whens0=>
next_state<=s1;
z<='1';
whens1=>
next_state<=s2;
z<='1';
whens2=>
next_state<=s3;
z<='0';
whens3=>
next_state<=s4;
z<='1';
whens4=>
next_state<=s0;
z<='0';
endcase;
endprocess;
endrtl;
10-16试用VHDL设计串行序列检测电路,当检测到连续四个和四个以上的1时,输出“1”,
否则输出“0”。
解:
程序设计如下:
libraryieee;
useieee.std_logic_1164.all;
entitymy_detectoris
port(
d:
instd_logic;
clk:
instd_logic;
z:
outstd_logic
);
endmy_detector;
architecturertlofmy_detectoris
typestate_typeis(s0,s1,s2,s3,s4);
signalcurrent_state,next_state:
state_type;
begin
synch:
process
begin
waituntilclk'eventandclk='1';
current_state<=next_state;
endprocess;
state_trans:
process(current_state)
begin
next_state<=current_state;
casecurrent_stateis
whens0=>
ifd='0'then
next_state<=s0;
z<='0';
else
next_state<=s1;
z<='0';
endif;
whens1=>
ifd='0'then
next_state<=s0;
z<='0';
else
next_state<=s2;
z<='0';
endif;
whens2=>
ifd='0'then
next_state<=s0;
z<='0';
else
next_state<=s3;
z<='0';
endif;
whens3=>
ifd='0'then
next_state<=s0;
z<='0';
else
next_state<=s4;
z<='1';
endif;
whens