StratixIVGTSchematicReviewWorksheet.docx

StratixIVGTSchematicReviewWorksheet.docx

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StratixIVGTSchematicReviewWorksheet

Stratix®IVGTDeviceSchematicReviewWorksheet

ThisdocumentisintendedtohelpyoureviewyourschematicandcomparethepinusageagainsttheStratixIVGTDeviceFamilyPinConnectionGuidelines（PDF）version1.3andotherreferencedliteratureforthisdevicefamily.ThetechnicalcontentisdividedintofocusareassuchasFPGApowersupplies,transceiverpowersuppliesandpinusage,configuration,FPGAI/O,andexternalmemoryinterfaces.

Withineachfocusarea,thereisatablethatcontainsthevoltageorpinnameforallofthededicatedanddualpurposepinsforthedevicefamily.Insomecases,thedevicedensityandpackagecombinationmaynotincludesomeofthepinsshowninthisworksheet,youshouldcrossreferencewiththepin-outfileforyourspecificdevice.Linkstothedevicepin-outfilesareprovidedatthetopofeachsection.

Beforeyoubeginusingthisworksheettoreviewyourschematicandcommittoboardlayout,Alterahighlyrecommends:

1）ReviewthelatestversionoftheStratixIVGTErrataSheet（PDF）andtheKnowledgeDatabaseforStratixIVDeviceKnownIssuesandStratixIVDeviceHandbookKnownIssues.

2）CompileyourdesignintheQuartus®IIsoftwaretocompletion.

Forexample,therearemanyI/OrelatedplacementrestrictionsandVCCIOrequirementsfortheI/Ostandardsusedinthedevice.Ifyoudonothaveacompleteproject,thenataminimumatoplevelprojectshouldbeusedwithallI/Opinsdefined,placed,andapplyalloftheconfigurableoptionsthatyouplantouse.AllI/Orelatedmegafunctionsshouldalsobeincludedintheminimalproject,including,butnotlimitedto,externalmemoryinterfaces,PLLs,altgx,altlvds,andaltddio.TheI/OAnalysistoolinthePinPlannercanthenbeusedontheminimalprojecttovalidatethepinoutinQuartusIIsoftwaretoassuretherearenoconflictswiththedevicerulesandguidelines.

WhenusingtheI/OAnalysistoolyoumustensuretherearenoerrorswithyourpinout.Additionally,youshouldcheckallwarningandcriticalwarningmessagestoevaluatetheirimpactonyourdesign.Youcanrightclickyourmouseoveranywarningorcriticalwarningmessageandselect“Help”.ThiswillbringopenanewHelpwindowwithfurtherinformationonthecauseofthewarning,andtheactionthatisrequired.

Forexample,thefollowingwarningisgeneratedwhenaPLLisdrivenbyaglobalnetworkwherethesourceisavaliddedicatedclockinputpin,butthepinisnotonededicatedtotheparticularPLL:

Warning:

PLL""inputclockinclk[0]isnotfullycompensatedandmayhavereducedjitterperformancebecauseitisfedbyanon-dedicatedinput

Info:

InputportINCLK[0]ofnode""isdrivenbyclock~clkctrlwhichisOUTCLKoutputportofClockControlBlocktypenodeclock~clkctrl

Thehelpfileprovidesthefollowing:

CAUSE:

ThespecifiedPLL'sinputclockisnotdrivenbyadedicatedinputpin.Asaresult,theinputclockdelaywillnotbefullycompensatedbythePLL.Additionally,jitterperformancedependsontheswitchingrateofotherdesignelements.Thiscanalsooccurifaglobalsignalassignmentisappliedtotheclockinputpin,whichforcestheclocktousethenon-dedicatedglobalclocknetwork.

ACTION:

Ifyouwantcompensationofthespecifiedinputclockorbetterjitterperformance,connecttheinputclockonlytoaninputpin,orassigntheinputpinonlytoadedicatedinputclocklocationforthePLL.Ifyoudonotwantcompensationofthespecifiedinputclock,thensetthePLLtoNoCompensationmode.

Whenassigningtheinputpintotheproperdedicatedclockpinlocation,refertoClockNetworksandPLLsinStratixIVDevices（PDF）fortheproperportmappingofdedicatedclockinputpinstoPLLs.

TherearemanyreportsavailableforuseafterasuccessfulcompilationorI/Oanalysis.Forexample,youcanusethe“AllPackagePins”and“I/OBankUsage”reportswithintheCompilation–Fitter–ResourceSectiontoseealloftheI/OstandardsandI/Oconfigurableoptionsthatareassignedtoallofthepinsinyourdesign,aswellasviewtherequiredVCCIOforeachI/Obank.Thesereportsmustmatchyourschematicpinconnections.

Thereviewtablehasthefollowingheading:

Plane/Signal

SchematicName

ConnectionGuidelines

Comments/Issues

Thefirstcolumn（Plane/Signal）liststheFPGAvoltageorsignalpinname.Youshouldonlyeditthiscolumntoremovededicatedordualpurposepinnamesthatarenotavailableforyourdevicedensityandpackageoption.

Thesecondcolumn（SchematicName）isforyoutoenteryourschematicname（s）forthesignal（s）orplaneconnectedtotheFPGApin（s）.

Thethirdcolumn（ConnectionGuidelines）shouldbeconsidered“readonly”asthiscontainsAltera’srecommendedconnectionguidelinesforthevoltageplaneorsignal.

Thefourthcolumn（Comments/Issues）isanareaprovidedasa“notepad”foryoutocommentonanydeviationsfromtheconnectionguidelines,andtoverifyguidelinesaremet.Inmanycasestherearenotesthatprovidefurtherinformationanddetailthatcomplimenttheconnectionguidelines.

Hereisanexampleofhowtheworksheetcanbeused:

Plane/Signal

SchematicName

ConnectionGuidelines

Comments/Issues

VCC

+0.95V

Connectedto+0.95Vplane,noisolationisnecessary.

Missinglowandmediumrangedecoupling,checkPDN.

SeeNotes（1-1）（1-2）.

LegalNote:

PLEASEREVIEWTHEFOLLOWINGTERMSANDCONDITIONSCAREFULLYBEFOREUSINGTHISSCHEMATICREVIEWWORKSHEET（“WORKSHEET”）PROVIDEDTOYOU.BYUSINGTHISWORKSHEET,YOUINDICATEYOURACCEPTANCEOFSUCHTERMSANDCONDITIONS,WHICHCONSTITUTETHELICENSEAGREEMENT（"AGREEMENT"）BETWEENYOUANDALTERACORPORATIONORITSAPPLICABLESUBSIDIARIES（"ALTERA"）.

1.SubjecttothetermsandconditionsofthisAgreement,Alteragrantstoyou,fornoadditionalfee,anon-exclusiveandnon-transferablerighttousethisWorksheetforthesolepurposeofverifyingthevalidityofthepinconnectionsofanAlteraprogrammablelogicdevice-baseddesign.YoumaynotusethisWorksheetforanyotherpurpose.TherearenoimpliedlicensesgrantedunderthisAgreement,andallrights,exceptforthosegrantedunderthisAgreement,remainwithAltera.

2.Alteradoesnotguaranteeorimplythereliability,orserviceability,ofthisWorksheetorotheritemsprovidedaspartofthisWorksheet.ThisWorksheetisprovided'ASIS'.ALTERADISCLAIMSALLWARRANTIES,EXPRESSORIMPLIED,INCLUDINGTHEIMPLIEDWARRANTIESOFMERCHANTABILITY,FITNESSFORAPARTICULARPURPOSE,ANDNON-INFRINGEMENT.ALTERAHASNOOBLIGATIONTOPROVIDEYOUWITHANYSUPPORTORMAINTENANCE.

3.InnoeventshalltheaggregateliabilityofAlterarelatingtothisAgreementorthesubjectmatterhereofunderanylegaltheory（whetherintort,contract,orotherwise）,exceedOneHundredUS Dollars（US$100.00）.InnoeventshallAlterabeliableforanylostrevenue,lostprofits,orotherconsequential,indirect,orspecialdamagescausedbyyouruseofthisWorksheetevenifadvisedofthepossibilityofsuchdamages.

4.ThisAgreementmaybeterminatedbyeitherpartyforanyreasonatanytimeupon30-days’priorwrittennotice.ThisAgreementshallbegovernedbythelawsoftheStateofCalifornia,withoutregardtoconflictoflaworchoiceoflawprinciples.YouagreetosubmittotheexclusivejurisdictionofthecourtsintheCountyofSantaClara,StateofCaliforniafortheresolutionofanydisputeorclaimarisingoutoforrelatingtothisAgreement.Thepartiesherebyagreethatthepartywhoisnotthesubstantiallyprevailingpartywithrespecttoadispute,claim,orcontroversyrelatingtothisAgreementshallpaythecostsactuallyincurredbythesubstantiallyprevailingpartyinrelationtosuchdispute,claim,orcontroversy,includingattorneys'fees.FailuretoenforceanytermorconditionofthisAgreementshallnotbedeemedawaiveroftherighttolaterenforcesuchtermorconditionoranyothertermorconditionoftheAgreement.

BYUSINGTHISWORKSHEET,YOUACKNOWLEDGETHATYOUHAVEREADTHISAGREEMENT,UNDERSTANDIT,ANDAGREETOBEBOUNDBYITSTERMSANDCONDITIONS.YOUANDALTERAFURTHERAGREETHATITISTHECOMPLETEANDEXCLUSIVESTATEMENTOFTHEAGREEMENTBETWEENYOUANDALTERA,WHICHSUPERSEDESANYPROPOSALORPRIORAGREEMENT,ORALORWRITTEN,ANDANYOTHERCOMMUNICATIONSBETWEENYOUANDALTERARELATINGTOTHESUBJECTMATTEROFTHISAGREEMENT.

Index

SectionI:

Power

SectionII:

Configuration

SectionIII:

Transceiver

SectionIV:

I/O

a:

ClockPins

b:

DedicatedandDualPurposePins

c:

DualPurposeDifferentialI/Opins

SectionV:

ExternalMemoryInterfacePins

a:

DDR/2InterfacePins

b:

DDR/2TerminationGuidelines

c:

DDR3InterfacePins

d:

DDR3TerminationGuidelines

e:

QDRII/+Interfacepins

f:

QDRII/+TerminationGuidelines

SectionVI:

DocumentRevisionHistory

SectionI:

Power

StratixIVRecommendedReferenceLiterature/ToolList

StratixIVPinOutFiles

StratixIVGTDeviceFamilyPinConnectionGuidelines（PDF）

StratixIVEarlyPowerEstimator

StratixIVEarlyPowerEstimatorUserGuide（PDF）

PowerDeliveryNetwork（PDN）ToolForStratixIVDevices

Device-SpecificPowerDeliveryNetwork（PDN）ToolUserGuide（PDF）

PowerPlayPowerAnalyzerSupportResources

AlteraBoardDesignResourceCenter（Generalboarddesignguidelines,PDNdesign,isolation,tools,andmore）

AN583:

DesigningPowerIsolationFilterswithFerriteBeadsforAlteraFPGAs（PDF）

AN597:

GettingStartedFlowforBoardDesigns（PDF）

StratixIVGTErrataSh