步行街道交通等控制电路的设计.docx
《步行街道交通等控制电路的设计.docx》由会员分享，可在线阅读，更多相关《步行街道交通等控制电路的设计.docx（18页珍藏版）》请在冰豆网上搜索。
步行街道交通等控制电路的设计
步行街道交通等控制电路的设计
整体结构图
libraryIEEE;
useIEEE.STD_LOGIC_1164.ALL;
useIEEE.STD_LOGIC_UNSIGNED.ALL;
entitytraffic_topis
Port（clk,clear,nclear,clkadd,nclkadd,clksub,nclksub,pre_set,
human_set,rst,request,nrequest,clk_s:
inSTD_LOGIC;
Egreen,ered,eyellow,sgreen,sred:
outSTD_LOGIC）;
endtraffic_top;
architectureBehavioraloftraffic_topis
ComponentDITHER1is
PORT（CLEAR:
INSTD_LOGIC;
NCLEAR:
INSTD_LOGIC;
KEYOUT1:
OUTSTD_LOGIC）;
endcomponent;
ComponentDITHER2is
PORT（CLKADD:
INSTD_LOGIC;
NCLKADD:
INSTD_LOGIC;
KEYOUT2:
OUTSTD_LOGIC）;
endcomponent;
Componentdither3is
PORT（CLksub:
INSTD_LOGIC;
Nclksub:
INSTD_LOGIC;
KEYOUT3:
OUTSTD_LOGIC）;
Endcomponent;
Componentdither4is
PORT（request:
INSTD_LOGIC;
nrequest:
INSTD_LOGIC;
KEYOUT4:
OUTSTD_LOGIC）;
Endcomponent;
Componentcountis
PORT（CLK:
INSTD_LOGIC;
Keyout1:
INSTD_LOGIC;
Keyout2:
INSTD_LOGIC;
Keyout3:
INSTD_LOGIC;
PRE_SET:
INSTD_LOGIC;
HUMAN_SET:
INSTD_LOGIC;
RST:
INSTD_LOGIC;
GHUMAN_TIME:
OUTINTEGERRANGE31DOWNTO0;
GHUMAN_CLKT:
OUTINTEGERRANGE31DOWNTO0;
GVEHICLE_TIME:
OUTINTEGERRANGE31DOWNTO0）;
Endcomponent;
Componentlightis
PORT（SRED:
OUTSTD_LOGIC;
SGREEN:
OUTSTD_LOGIC;
ERED:
OUTSTD_LOGIC;
EGREEN:
OUTSTD_LOGIC;
EYELLOW:
OUTSTD_LOGIC;
pre_SET:
INSTD_LOGIC;
GHUMAN_TIME:
ININTEGERRANGE31DOWNTO0;
GHUMAN_CLKT:
ININTEGERRANGE31DOWNTO0;
GVEHICLE_TIME:
ININTEGERRANGE31DOWNTO0;
Keyout4:
INSTD_LOGIC;
CLK_s:
INSTD_LOGIC;
RST:
INSTD_LOGIC）;
Endcomponent;
BEGIN
U1:
dither1PORTMAP（clear,nclear,keyout1）;
U2:
dither2PORTMAP（clkadd,nclkadd,keyout2）;
U3:
dither3PORTMAP（clksub,nclksub,keyout3）;
u4:
dither4PORTMAP（request,nrequest,keyout4）;
U5:
countportmap（clk,keyout1,keyout2,keyout3,pre_set,human_set,
rst,ghuman_time,ghuman_clkt,gvehicle_time）;
U6:
lightportmap（ghuman_time,ghuman_clkt,gvehicle_time,keyout4,clk_s,rst,
Sred,sgreen,syellow,ered,egreen）;
EndBehavioral;
电路模块设计：
包含三部分去抖模块、计数模块、交通控制模块
（1）去抖模块
模块的语言设计
DITHER1（去抖模块1）VHDL源程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYDITHER1IS
PORT（clear:
INSTD_LOGIC;
nclear:
INSTD_LOGIC;
KEYOUT1:
OUTSTD_LOGIC）;
ENDDITHER1;
ARCHITECTUREBEHAVEOFDITHER1IS
SIGNALOUT1:
STD_LOGIC;
SIGNALOUT2:
STD_LOGIC;
BEGIN
OUT1<=NOT（OUT2ANDUPIN）;
OUT2<=NOT（OUT1ANDDOWNIN）;
KEYOUT<=OUT1;
ENDBEHAVE;
DITHER2（去抖模块2）VHDL源程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYDITHER2IS
PORT（clkadd:
INSTD_LOGIC;
nclkadd:
INSTD_LOGIC;
KEYOUT2:
OUTSTD_LOGIC）;
ENDDITHER2;
ARCHITECTUREBEHAVEOFDITHER2IS
SIGNALOUT1:
STD_LOGIC;
SIGNALOUT2:
STD_LOGIC;
BEGIN
OUT1<=NOT（OUT2ANDUPIN）;
OUT2<=NOT（OUT1ANDDOWNIN）;
KEYOUT<=OUT1;
ENDBEHAVE;
DITHER3（去抖模块3）VHDL源程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYDITHER3IS
PORT（clksub:
INSTD_LOGIC;
nclksub:
INSTD_LOGIC;
KEYOUT3:
OUTSTD_LOGIC）;
ENDDITHER3;
ARCHITECTUREBEHAVEOFDITHER3IS
SIGNALOUT1:
STD_LOGIC;
SIGNALOUT2:
STD_LOGIC;
BEGIN
OUT1<=NOT（OUT2ANDUPIN）;
OUT2<=NOT（OUT1ANDDOWNIN）;
KEYOUT<=OUT1;
ENDBEHAVE;
DITHER4（去抖模块4）VHDL源程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYDITHER4IS
PORT（request:
INSTD_LOGIC;
nrequest:
INSTD_LOGIC;
KEYOUT4:
OUTSTD_LOGIC）;
ENDDITHER4;
ARCHITECTUREBEHAVEOFDITHER4IS
SIGNALOUT1:
STD_LOGIC;
SIGNALOUT2:
STD_LOGIC;
BEGIN
OUT1<=NOT（OUT2ANDUPIN）;
OUT2<=NOT（OUT1ANDDOWNIN）;
KEYOUT<=OUT1;
ENDBEHAVE;
（2）设置计数模块
COUNT（计数模块）VHDL源程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYCOUNTIS
PORT（CLK:
INSTD_LOGIC;
Keyout1:
INSTD_LOGIC;
Keyout2:
INSTD_LOGIC;
Keyout3:
INSTD_LOGIC;
PRE_SET:
INSTD_LOGIC;
HUMAN_SET:
INSTD_LOGIC;
RST:
INSTD_LOGIC;
GHUMAN_TIME:
OUTINTEGERRANGE31DOWNTO0;
GHUMAN_CLKT:
OUTINTEGERRANGE31DOWNTO0;
GVEHICLE_TIME:
OUTINTEGERRANGE31DOWNTO0）;
ENDCOUNT;
ARCHITECTUREBEHAVEOFCOUNTIS
SIGNALHUMAN_TIME:
INTEGERRANGE31DOWNTO0;
SIGNALVEHICLE_TIME:
INTEGERRANGE31DOWNTO0;
SIGNALSSTATE:
STD_LOGIC_VECTOR（3DOWNTO0）;
SIGNALSCLK:
STD_LOGIC;
SIGNALDSCLK:
STD_LOGIC;
BEGIN
PROCESS（CLK）
SSTATE<="000"WHENPRE_SET='0'ELSE
HUMAN_SET&CLEAR&CLKSUB;
SCLK<=CLKADDORCLKSUBORCLEAR;
BEGIN
IF（CLK'EVENTANDCLK='1'）THEN
DSCLK<=SCLK;
ENDIF;
ENDPROCESS;
PROCESS（RST,CLEAR,DSCLK）
BEGIN
IF（RST='1'）THEN
VEHICLE_TIME<=8;
ELSIF（DSCLK'EVENTANDDSCLK='1'）THEN
CASESSTATEIS
WHEN"0100"=>VEHICLE_TIME<=0;
WHEN"0101"=>VEHICLE_TIME<=0;
WHEN"0110"=>VEHICLE_TIME<=0;
WHEN"0111"=>VEHICLE_TIME<=0;
WHEN"0001"=>VEHICLE_TIME<=VEHICLE_TIME-1;
WHEN"0010"=>VEHICLE_TIME<=VEHICLE_TIME+1;
WHENOTHERS=>VEHICLE_TIME<=VEHICLE_TIME;
ENDCASE;
ENDIF;
ENDPROCESS;
PROCESS（CLEAR,DSCLK）
BEGIN
IF（RST='1'）THEN
HUMAN_TIME<=4;
ELSIF（DSCLK'EVENTANDDSCLK='1'）THEN
CASESSTATEIS
WHEN"1100"=>HUMAN_TIME<=0;
WHEN"1101"=>HUMAN_TIME<=0;
WHEN"1110"=>HUMAN_TIME<=0;
WHEN"1111"=>HUMAN_TIME<=0;
WHEN"1001"=>HUMAN_TIME<=HUMAN_TIME-1;
WHEN"1010"=>HUMAN_TIME<=HUMAN_TIME+1;
WHENOTHERS=>HUMAN_TIME<=HUMAN_TIME;
ENDCASE;
ENDIF;
ENDPROCESS;
PROCESS（PRE_SET,RST）
BEGIN
IF（RST='1'）THEN
GHUMAN_TIME<=5;
GHUMAN_CLKT<=7;
GVEHICLE_TIME<=15;
ELSIF（PRE_SET'EVENTANDPRE_SET='0'）THEN
GHUMAN_TIME<=HUMAN_TIME+1;
GHUMAN_CLKT<=HUMAN_TIME+3;
GVEHICLE_TIME<=HUMAN_TIME+VEHICLE_TIME+3;
ENDIF;
ENDPROCESS;
ENDBEHAVE;
（3）交通灯控制模块
LIGHT（交通灯控制模块）VHD源程序
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYLIGHTIS
PORT（SRED:
OUTSTD_LOGIC;——行人方向红灯
SGREEN:
OUTSTD_LOGIC;——行人方向绿灯
ERED:
OUTSTD_LOGIC;——车辆方向红灯
EGREEN:
OUTSTD_LOGIC;——车辆方向绿灯
EYELLOW:
OUTSTD_LOGIC;——车辆方向黄灯
PRE_SET:
INSTD_LOGIC;——预置有效信号输入
GHUMAN_TIME:
ININTEGERRANGE31DOWNTO0;
——行人通行时间
GHUMAN_CLKT:
ININTEGERRANGE31DOWNTO0;
——行人方向信号灯闪烁时间
GVEHICLE_TIME:
ININTEGERRANGE31DOWNTO0;
——车辆通行时间
KEYOUT4:
INSTD_LOGIC;——请求信号输入
CLK_S:
INSTD_LOGIC;——时钟信号
RST:
INSTD_LOGIC）;——复位信号
ENDLIGHT;
ARCHITECTUREBEHAVEOFLIGHTIS
TYPEIN_STATESIS（ST0,ST1,ST2,ST3,ST4）;
SIGNALCURRENT_STATE:
IN_STATES;
SIGNALNEXT_STATE:
IN_STATES;
SIGNALSTART:
STD_LOGIC;
SIGNALSIG:
INTEGERRANGE31DOWNTO0;
BEGIN
PROCESS（CURRENT_STATE,RST）
BEGIN
IF（RST='1'ORCURRENT_STATE=ST0）THEN
START<='0';
ELSE
START<='1';
ENDIF;
ENDPROCESS;
A:
PROCESS（START,CLK）
BEGIN
IF（RST='1'）THEN
SIG<=0;
ELSIF（CLK'EVENTANDCLK='1'）THEN
IF（START='1'）THEN
IF（SIG=GVEHICLE_TIME）THEN
SIG<=0;
ELSE
SIG<=SIG+1;
ENDIF;
ELSE
SIG<=0;
ENDIF;
ENDIF;
ENDPROCESSA;
PROCESS（RST,CLK）
BEGIN
IF（RST='1'）THEN
CURRENT_STATE<=ST0;
ELSIF（CLK'EVENTANDCLK='1'）THEN
CURRENT_STATE<=NEXT_STATE;
ENDIF;
ENDPROCESS;
PROCESS（CLK,CURRENT_STATE）
BEGIN
CASECURRENT_STATEIS
WHENST0=>ERED<='0';
EGREEN<='1';EYELLOW<='1';SRED<='0';SGREEN<='0';
IF（REQUEST='1'ANDGT_SET='0'）THEN
NEXT_STATE<=ST1;
ELSE
NEXT_STATE<=ST0;
ENDIF;
WHENST1=>ERED<='0';
EGREEN<='0';EYELLOW<='1';SRED<='1';SGREEN<='0';
IF（SIG=1）THEN
NEXT_STATE<=ST2;
ELSE
NEXT_STATE<=ST1;
ENDIF;
WHENST2=>ERED<='1';
EGREEN<='0';EYELLOW<='0';SRED<='0';SGREEN<='1';
IF（SIG=GHUMAN_TIME）THEN
NEXT_STATE<=ST3;
ELSE
NEXT_STATE<=ST2;
ENDIF;
WHENST3=>ERED<='1';
EGREEN<='0';EYELLOW<='0';SRED<='0';SGREEN<=NOTCLK;
IF（SIG=GHUMAN_CLKT）THEN
NEXT_STATE<=ST4;
ELSE
NEXT_STATE<=ST3;
ENDIF;
WHENST4=>ERED<='0';
EGREEN<='1';EYELLOW<='0';SRED<='1';SGREEN<='0';
IF（SIG=GVEHICLE_TIME）THEN
NEXT_STATE<=ST0;
ELSE
NEXT_STATE<=ST4;
ENDIF;
WHENOTHERS=>ERED<='0';EGREEN<='1';EYELLOW<='0';
SRED<='1';SGREEN<='0';NEXT_STATE<=ST3;
ENDCASE;
ENDPROCESS;
ENDBEHAVE;
三）系统仿真
（1）去抖模块的仿真
其余两个仅输入信号的名称不同，仿真波形相同。
（2）设置计数模块的仿真图
（3）交通灯控制模块的仿真
若用qurtus软件，则仿真波形如下：
1、去抖模块的仿真：
2、计数模块的仿真：
3、交通灯控制模块的仿真：
4、综合仿真：
升级会员 