可编程逻辑报告.docx
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可编程逻辑报告
可编程逻辑报告
3-2:
逻辑门电
用VHDL设计实现如下逻辑表达式所对应的逻辑门电路:
F0=AB+BC+
X
F1=ABC+
F2=A
B
C+
F3=
+ABD
BCD
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_2is
port(a,b,c,d:
instd_logic;
f:
outstd_logic_vector(3downto0));
ende3_2;
architecturebehavofe3_2is
begin
f(0)<=(aandb)or(bandc)or(notbandnotc);
f
(1)<=(aandbandc)ornot(notaornotbornotc);
f
(2)<=(axorbxorc)or(not(d)and(aorc));
f(3)<=not((aandb)xor(candd))or((aandbandd)xor(bandcandd));
endbehav;
仿真波形:
3-4:
8线-3线优先编码器
用VHDL设计8线-3线优先编码器,编码器输出编码为反码输出。
优先编码器的编码输入和输出均为低电平,且有使能输入和使能输出的功能。
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_4is
port(sin:
instd_logic;
i:
instd_logic_vector(7downto0);
a:
outstd_logic_vector(2downto0);
e,s:
outstd_logic);
end;
architecturebehavofe3_4is
begin
process(sin,i)
begin
ifsin='1'then
a<="111";e<='1';s<='1';
else
ifi(7)='0'then
a<="000";e<='0';s<='1';
elsifi(6)='0'then
a<="001";e<='0';s<='1';
elsifi(5)='0'then
a<="010";e<='0';s<='1';
elsifi(4)='0'then
a<="011";e<='0';s<='1';
elsifi(3)='0'then
a<="100";e<='0';s<='1';
elsifi
(2)='0'then
a<="101";e<='0';s<='1';
elsifi
(1)='0'then
a<="110";e<='0';s<='1';
elsifi(0)='0'then
a<="111";e<='0';s<='1';
else
a<="111";e<='1';s<='0';
endif;
endif;
endprocess;
endbehav;
仿真波形:
3-6:
用VHDL设计半导体数码管的七段显示译码器
半导体数码管有共阳极和共阴极两种类型,共阴极是7个发光二极管的阴极接在一起,通常是接地,而7个阳极是独立的;共阳极是7个发光二极管的阳极接在一起,通常是经过限流电阻后接+5V电源,而阴极是独立的。
共阴极数码管需要有输出高电平有效的译码器去驱动,而共阳极数码管则需要有输出低电平有效的译码器去驱动。
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_6is
port(hex:
instd_logic_vector(3downto0);
segment:
outstd_logic_vector(6downto0));
ende3_6;
architecturebehavofe3_6is
begin
withhexselect
segment<="1111001"when"0001",
"0100100"when"0010",
"0110000"when"0011",
"0011001"when"0100",
"0010010"when"0101",
"0000010"when"0110",
"1111000"when"0111",
"0000000"when"1000",
"0010000"when"1001",
"1000000"whenothers;
endbehav;
仿真波形:
3-7:
用VHDL设计4选1数据选择器
4选1数据选择器有四个输入D3—D0,一个输出F。
还有两个地址选择输入A0、A1。
当A0和A1为不同代码时,D3—D0从不同的通道数据送至输出端F。
同时,使能端E为低电平是选择器才能正常工作。
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_7is
port(d:
instd_logic_vector(3downto0);
a:
instd_logic_vector(1downto0);
e:
instd_logic;
f:
outstd_logic);
ende3_7;
architecturebehavofe3_7is
begin
process(e,a,d)
begin
ife='0'then
caseais
when"00"=>f<=d(0);
when"01"=>f<=d
(1);
when"10"=>f<=d
(2);
when"11"=>f<=d(3);
whenothers=>f<='Z';
endcase;
endif;
endprocess;
endbehav;
仿真波形:
3-10:
用VHDL设计两总线数据分配器
数据分配器是将一路数据分配到多路通道中去的器件,简称DEMUX。
其电路是单输入多输出式。
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_10is
port(sel:
instd_logic;
a,b:
instd_logic_vector(7downto0);
mux_out:
outstd_logic_vector(7downto0));
end;
architecturebehavofe3_10is
begin
process(sel,a,b)
begin
ifsel='1'then
mux_out<=a;
else
mux_out<=b;
endif;
endprocess;
endbehav;
仿真波形:
3-12:
用VHDL设计8位有符号的数值比较器
数值比较器是用来比较两个数据之间数值关系的电路。
有符号数的比较,要先判断符号位,如果均为正数,则数据位大的其数值较大;如果均为负数,则数据位较小的其数值较大;如果符号位不同,则正数大于负数。
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_12is
port(a,b:
instd_logic_vector(7downto0);
gt,eq,lt:
outstd_logic);
end;
architecturebehavofe3_12is
signalsab:
std_logic_vector(1downto0);
begin
sab<=a(7)&b(7);
process(sab,a,b)
begin
case(sab)is
when"00"=>
ifa(6downto0)>b(6downto0)thengt<='1';eq<='0';lt<='0';
elsifa(6downto0)=b(6downto0)thengt<='0';eq<='1';lt<='0';
elsegt<='0';eq<='0';lt<='1';
endif;
when"01"=>gt<='1';eq<='0';lt<='0';
when"10"=>gt<='0';eq<='0';lt<='1';
when"11"=>
ifa(6downto0)>b(6downto0)thengt<='0';eq<='0';lt<='1';
elsifa(6downto0)=b(6downto0)thengt<='0';eq<='1';lt<='0';
elsegt<='1';eq<='0';lt<='0';
endif;
whenothers=>gt<='0';eq<='0';lt<='0';
endcase;
endprocess;
endbehav;
仿真波形:
3-13:
8位二进制数的加法器
算术运算单元电路是构成处理器CPU的算术逻辑单元(ALU)的一个重要组成部分。
通常有加、减、乘、除4种运算。
8位二进制数的加法器可以由8个全加器级联构成。
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_13is
port(a,b:
instd_logic_vector(7downto0);
s:
outstd_logic_vector(7downto0);
co:
outstd_logic);
ende3_13;
architecturebehavioralofe3_13is
signalta,tb:
std_logic_vector(8downto0);
signalts:
std_logic_vector(8downto0);
begin
ta<='0'&a;
tb<='0'&b;
ts<=ta+tb;
s<=ts(7downto0);
co<=ts(8);
endbehavioral;
仿真波形
3-14:
用VHDL设计D触发器
触发器是能够存储一位二进制数的逻辑电路,是时序逻辑电路的基本单元电路。
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_14is
port(d:
instd_logic;
clk:
instd_logic;
q:
outstd_logic);
ende3_14;
architecturebehavioralofe3_14is
begin
process(clk)
begin
ifclk'eventandclk='1'then
q<=d;
endif;
endprocess;
endbehavioral;
仿真波形
3-15:
用VHDL设计具有异步复位和同步置位的D触发器
对于时序电路的控制,通常分为同步方式和异步方式。
同步方式是指控制信号只有在时钟信号有效时才起作用,异步方式是指控制系统起作用不需要时钟信号有效。
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_15is
port(d:
instd_logic;
clk:
instd_logic;
clr,set:
instd_logic;
q:
outstd_logic);
ende3_15;
architecturebehavioralofe3_15is
begin
process(clk,clr,set)
begin
ifclr='1'thenq<='0';
elsifrising_edge(clk)then
ifset='1'then
q<='1';
else
q<=d;
endif;
endif;
endprocess;
endbehavioral;
仿真波形
3-17:
用VHDL设计8位锁存器
参考程序
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_17is
port(d:
instd_logic_vector(7downto0);
le:
instd_logic;
q:
outstd_logic_vector(7downto0));
ende3_17;
architecturebehavioralofe3_17is
signalqin:
std_logic_vector(7downto0);
begin
p1:
process(d)
begin
ifle='1'then
qin<=d;
endif;
endprocessp1;
p2:
process(le)
begin
iffalling_edge(le)then
q<=qin;
endif;
endprocessp2;
endbehavioral;
仿真波形
3-21:
用VHDL设计十进制计数器
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_21is
port(en,clk:
instd_logic;
q:
outstd_logic_vector(3downto0);
qcc:
outstd_logic);
ende3_21;
architecturebehavioralofe3_21is
signalqtemp:
std_logic_vector(3downto0);
begin
process(clk,en)
begin
ifclk'eventandclk='1'then
ifen='1'then
ifqtemp="1001"then
qtemp<="0000";
else
qtemp<=qtemp+'1';
endif;
endif;
endif;
endprocess;
q<=qtemp;
qcc<=qtemp(3)andqtemp
(2)andqtemp(0)andqtemp(0);
endbehavioral;
仿真波形
3-23用VHDL设计实现交通灯控制器的Mealy型状态机
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_23is
port(reset,clk:
instd_logic;
t1,t2,t3:
instd_logic;
r,g,y:
outstd_logic);
ende3_23;
architecturebehavioralofe3_23is
typestate_typeis(red,green,yellow);
signalstate,next_state:
state_type;
begin
sync_ptoc:
process(clk)
begin
if(clk'eventandclk='1')then
if(reset='1')then
state<=red;
else
state<=next_state;
endif;
endif;
endprocess;
--mealystatemachine-outputsbasedonstateandinputs
output_decode:
process(state,t1,t2,t3)
begin
if(state=redandt1='0')then
r<='1';g<='0';y<='0';
elsif(state=greenandt2='0')then
r<='0';g<='1';y<='0';
elsif(state=yellowandt3='0')then
r<='0';g<='0';y<='1';
endif;
endprocess;
next_state_decode:
process(state,t1,t2,t3)
begin
next_state<=state;
case(state)is
whenred=>
ift1='1'then
next_state<=green;
endif;
whengreen=>
ift2='1'then
next_state<=yellow;
endif;
whenyellow=>
next_state<=red;
whenothers=>
next_state<=red;
endcase;
endprocess;
endbehavioral;
仿真波形
3-24用VHDL设计实现空调系统的控制器的Moore型状态机
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitye3_24is
port(reset,clk:
instd_logic;
high,low:
instd_logic;
cold,heat:
outstd_logic);
ende3_24;
architecturebehavofe3_24is
typestate_typeis(too_high,too_low,well_situated);
signalstate,next_state:
state_type;
begin
sync_proc:
process(clk)
begin
if(clk'eventandclk='1')then
if(reset='1')then
state<=well_situated;
else
state<=next_state;
endif;
endif;
endprocess;
--moorestatemachine
output_decode:
process(state)
begin
ifstate=too_highthen
cold<='1';heat<='0';
elsifstate=too_lowthen
cold<='0';heat<='1';
elsifstate=well_situatedthen
cold<='0';heat<='0';
endif;
endprocess;
next_state_decode:
process(state,high,low)
begin
next_state<=state;
case(state)is
whenwell_situated=>
ifhigh='1'then
next_state<=too_high;
endif;
iflow='1'then
next_state<=too_low;
endif;
whentoo_high=>
ifhigh='1'then
next_state<=too_high;
else
next_state<=well_situated;
endif;
whentoo_low=>
iflow='1'then
next_state<=too_low;
else
next_state<=well_situated;
endif;
whenothers=>
next_state<=well_situated;
endcase;
endprocess;
endbehav;
仿真波形
3-25用VHDL设计8*8的ROM
用VHDL设计ROM主要需解决两个问题。
一个是ROM的初始化问题;另一个是ROM的定义问题。
参考程序:
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;