可编程逻辑报告.docx

1、可编程逻辑报告可编程逻辑报告3-2:逻辑门电用VHDL设计实现如下逻辑表达式所对应的逻辑门电路：F0=AB+BC+XF1=ABC+F2=ABC+F3=+ABDBCD参考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_2 is port(a,b,c,d: in std_logic; f : out std_logic_vector(3 downto 0);end e3_2;architecture behav of

2、e3_2 is begin f(0) =(a and b) or (b and c) or (not b and not c); f(1) =(a and b and c) or not(not a or not b or not c); f(2) =(a xor b xor c) or (not(d) and (a or c); f(3) =not(a and b ) xor (c and d)or (a and b and d) xor (b and c and d);end behav;仿真波形：3-4：8线-3线优先编码器用VHDL设计8线-3线优先编码器,编码器输出编码为反码输出。优

3、先编码器的编码输入和输出均为低电平，且有使能输入和使能输出的功能。参考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_4 isport(sin: in std_logic; i: in std_logic_vector(7 downto 0); a: out std_logic_vector(2 downto 0); e,s: out std_logic );end;architecture behav of e3

4、_4 is begin process(sin,i) begin if sin =1 then a=111; e=1; s=1; else if i(7)=0 then a=000; e=0; s=1; elsif i(6)=0 then a=001;e=0;s=1; elsif i(5)=0 then a=010;e=0;s=1; elsif i(4)=0 then a=011;e=0;s=1; elsif i(3)=0 then a=100;e=0;s=1; elsif i(2)=0 then a=101;e=0;s=1; elsif i(1)=0 then a=110;e=0;s=1;

5、elsif i(0)=0 then a=111;e=0;s=1; else a=111;e=1;s=0; end if; end if; end process; end behav;仿真波形：3-6：用VHDL设计半导体数码管的七段显示译码器半导体数码管有共阳极和共阴极两种类型，共阴极是7个发光二极管的阴极接在一起，通常是接地，而7个阳极是独立的；共阳极是7个发光二极管的阳极接在一起，通常是经过限流电阻后接+5V电源，而阴极是独立的。共阴极数码管需要有输出高电平有效的译码器去驱动，而共阳极数码管则需要有输出低电平有效的译码器去驱动。参考程序：library ieee;use ieee.std

6、_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_6 is port(hex: in std_logic_vector(3 downto 0); segment: out std_logic_vector(6 downto 0);end e3_6;architecture behav of e3_6 isbegin with hex select segmentfffff=Z; end case; end if; end process;end behav;仿真波形：3-

7、10：用VHDL设计两总线数据分配器数据分配器是将一路数据分配到多路通道中去的器件，简称DEMUX。其电路是单输入多输出式。参考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_10 is port(sel: in std_logic; a,b: in std_logic_vector(7 downto 0); mux_out: out std_logic_vector(7 downto 0);end;archite

8、cture behav of e3_10 is begin process(sel,a,b) begin if sel=1 then mux_out=a; else mux_out=b; end if; end process;end behav;仿真波形：3-12：用VHDL设计8位有符号的数值比较器数值比较器是用来比较两个数据之间数值关系的电路。有符号数的比较，要先判断符号位，如果均为正数，则数据位大的其数值较大；如果均为负数，则数据位较小的其数值较大；如果符号位不同，则正数大于负数。参考程序：library ieee;use ieee.std_logic_1164.all;use iee

9、e.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_12 is port(a,b: in std_logic_vector(7 downto 0); gt,eq,lt: out std_logic);end;architecture behav of e3_12 is signal sab: std_logic_vector(1 downto 0);beginsab if a(6 downto 0) b(6 downto 0) then gt=1; eq=0; lt=0; elsif a(6 downto 0) = b

10、(6 downto 0) then gt=0; eq=1; lt=0; else gt=0;eq=0;lt gt=1;eq=0;lt gt=0;eq=0;lt if a(6 downto 0) b(6 downto 0) then gt=0;eq=0;lt=1; elsif a(6 downto 0) = b(6 downto 0) then gt=0;eq=1;lt=0; else gt=1; eq=0; lt gt=0;eq=0;lt=0; end case; end process;end behav; 仿真波形：3-13：8位二进制数的加法器算术运算单元电路是构成处理器CPU的算术逻辑

11、单元（ALU）的一个重要组成部分。通常有加、减、乘、除 4种运算。8位二进制数的加法器可以由8个全加器级联构成。参考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_13 is port(a,b: in std_logic_vector(7 downto 0); s: out std_logic_vector(7 downto 0); co: out std_logic);end e3_13;architecture

12、 behavioral of e3_13 issignal ta,tb: std_logic_vector(8 downto 0);signal ts: std_logic_vector(8 downto 0);beginta=0&a;tb=0&b;ts=ta+tb;s=ts(7 downto 0);co=ts(8);end behavioral;仿真波形3-14：用VHDL设计D触发器触发器是能够存储一位二进制数的逻辑电路，是时序逻辑电路的基本单元电路。参考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith

13、.all;use ieee.std_logic_unsigned.all;entity e3_14 is port(d: in std_logic; clk: in std_logic; q: out std_logic);end e3_14;architecture behavioral of e3_14 isbegin process(clk) begin if clkevent and clk=1 then q=d; end if; end process;end behavioral;仿真波形3-15：用VHDL设计具有异步复位和同步置位的D触发器对于时序电路的控制，通常分为同步方式和

14、异步方式。同步方式是指控制信号只有在时钟信号有效时才起作用，异步方式是指控制系统起作用不需要时钟信号有效。参考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_15 is port(d: in std_logic; clk: in std_logic; clr,set: in std_logic; q: out std_logic);end e3_15;architecture behavioral of e3_15

15、 isbegin process(clk,clr,set) begin if clr=1 then q=0; elsif rising_edge(clk) then if set=1 then q=1; else q=d; end if; end if; end process;end behavioral;仿真波形3-17：用VHDL设计8位锁存器参考程序library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_17 is po

16、rt(d: in std_logic_vector(7 downto 0); le: in std_logic; q: out std_logic_vector(7 downto 0);end e3_17;architecture behavioral of e3_17 issignal qin: std_logic_vector(7 downto 0);begin p1: process(d) begin if le=1then qin=d; end if; end process p1; p2: process(le) begin if falling_edge(le) then q= q

17、in; end if; end process p2;end behavioral;仿真波形3-21：用VHDL设计十进制计数器参考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_21 is port(en,clk: in std_logic; q: out std_logic_vector(3 downto 0); qcc: out std_logic);end e3_21;architecture behavi

18、oral of e3_21 issignal qtemp: std_logic_vector(3 downto 0);begin process(clk,en) begin if clkevent and clk=1then if en=1then if qtemp=1001then qtemp=0000; else qtemp=qtemp+1; end if; end if; end if; end process;q=qtemp;qcc=qtemp(3) and qtemp(2) and qtemp(0) and qtemp(0);end behavioral;仿真波形3-23 用VHDL

19、设计实现交通灯控制器的Mealy型状态机参考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_23 is port (reset,clk: in std_logic; t1,t2,t3: in std_logic; r,g,y: out std_logic);end e3_23;architecture behavioral of e3_23 is type state_type is (red,green,yell

20、ow); signal state,next_state:state_type;beginsync_ptoc: process(clk) begin if (clkevent and clk =1)then if(reset =1)then state = red; else state = next_state; end if; end if;end process;-mealy state machine-outputs based on state and inputsoutput_decode: process(state,t1,t2,t3)begin if(state =red an

21、d t1 =0)then r=1; g=0; y=0; elsif (state = green and t2 = 0)then r=0; g=1; y=0; elsif (state = yellow and t3 = 0)then r=0; g=0; y=1; end if;end process;next_state_decode: process(state,t1,t2,t3)begin next_state if t1 =1 then next_state if t2 =1 then next_state next_state next_state= red; end case; e

22、nd process;end behavioral;仿真波形3-24 用VHDL设计实现空调系统的控制器的Moore型状态机参考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;use ieee.std_logic_unsigned.all;entity e3_24 is port (reset,clk: in std_logic; high,low: in std_logic; cold,heat: out std_logic);end e3_24;architecture behav of e3

23、_24 istype state_type is(too_high, too_low,well_situated);signal state, next_state: state_type;beginsync_proc:process(clk) begin if(clkevent and clk=1)then if(reset=1)then state= well_situated; else state= next_state; end if; end if; end process;-moore state machineoutput_decode: process(state) begi

24、n if state = too_high then cold=1; heat=0; elsif state = too_low then cold=0; heat=1; elsif state = well_situated then cold=0; heat=0; end if ; end process;next_state_decode: process(state,high,low) begin next_state if high=1then next_state = too_high; end if; if low=1then next_state if high=1then next_state= too_high; else next_state if low=1then next_state = too_low; else next_state next_state = well_situated; end case; end process;end behav;仿真波形3-25用VHDL设计8*8的ROM 用VHDL设计ROM主要需解决两个问题。一个是ROM的初始化问题；另一个是ROM的定义问题。 参考程序：library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;