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PicroBlaze源代码.docx

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PicroBlaze源代码.docx

PicroBlaze源代码

--PicoBlaze

--

--Constant（K）CodedProgrammableStateMachineforSpartan-3Devices.

--AlsosuitableforusewithVirtex-IIandVirtex-IIPROdevices.

--

--IncludesadditionalcodeforenhancedVHDLsimulation.

--

--Version:

1.30

--VersionDate:

14thJune2004

--Reasons:

AvoidissuecausedwhenENABLEINTERRUPTisusedwheninterruptsare

--alreadyenabledwhenananinterruptinputisapplied.

--ImproveddesignforfasterZEROandCARRYflaglogic

--

--

--PreviousVersion:

1.20

--VersionDate:

9thJuly2003

--

--Startofdesignentry:

19thMay2003

--

--KenChapman

--XilinxLtd

--BenchmarkHouse

--203BrooklandsRoad

--Weybridge

--SurreyKT13ORH

--UnitedKingdom

--

--chapman@

--

--InstructiondisassemblyconceptinspiredbytheworkofProf.Dr.-Ing.BernhardLang.

--UniversityofAppliedSciences,Osnabrueck,Germany.

--

------------------------------------------------------------------------------------

--

--NOTICE:

--

--CopyrightXilinx,Inc.2003.Thiscodemaybecontainportionspatentedbyother

--thirdparties.Byprovidingthiscoreasonepossibleimplementationofastandard,

--Xilinxismakingnorepresentationthattheprovidedimplementationofthisstandard

--isfreefromanyclaimsofinfringementbyanythirdparty.Xilinxexpressly

--disclaimsanywarrantywithrespecttotheadequacyoftheimplementation,including

--butnotlimitedtoanywarrantyorrepresentationthattheimplementationisfree

--fromclaimsofanythirdparty.Furthermore,Xilinxisprovidingthiscoreasa

--courtesytoyouandsuggeststhatyoucontactallthirdpartiestoobtainthe

--necessaryrightstousethisimplementation.

--

------------------------------------------------------------------------------------

--

--Formatofthisfile.

--

--ThisfilecontainsthedefinitionofKCPSM3asonecompletemodulewithsections

--createdusinggenerateloops.This'flat'approachhasbeenadoptedtodecrease

--thetimetakentoloadthemoduleintosimulatorsandthesynthesisprocess.

--

--ThemoduledefinestheimplementationofthelogicusingXilinxprimitives.

--Theseensurepredictablesynthesisresultsandmaximisethedensityoftheimplementation.

--TheUnisimLibraryisusedtodefineXilinxprimitives.Itisalsousedduring

--simulation.Thesourcecanbeviewedat%XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd

--

------------------------------------------------------------------------------------

--

--Librarydeclarations

--

--StandardIEEElibraries

--

libraryIEEE;

useIEEE.STD_LOGIC_1164.ALL;

useIEEE.STD_LOGIC_ARITH.ALL;

useIEEE.STD_LOGIC_UNSIGNED.ALL;

libraryunisim;

useunisim.vcomponents.all;

--

------------------------------------------------------------------------------------

--

--MainEntityforKCPSM3

--

entitykcpsm3is

Port（address:

outstd_logic_vector（9downto0）;

instruction:

instd_logic_vector（17downto0）;

port_id:

outstd_logic_vector（7downto0）;

write_strobe:

outstd_logic;

out_port:

outstd_logic_vector（7downto0）;

read_strobe:

outstd_logic;

in_port:

instd_logic_vector（7downto0）;

interrupt:

instd_logic;

interrupt_ack:

outstd_logic;

reset:

instd_logic;

clk:

instd_logic）;

endkcpsm3;

--

------------------------------------------------------------------------------------

--

--StartofMainArchitectureforKCPSM3

--

architecturelow_level_definitionofkcpsm3is

--

------------------------------------------------------------------------------------

--

--SignalsusedinKCPSM3

--

------------------------------------------------------------------------------------

--

--Fundamentalcontrolanddecodesignals

--

signalt_state:

std_logic;

signalnot_t_state:

std_logic;

signalinternal_reset:

std_logic;

signalreset_delay:

std_logic;

signalmove_group:

std_logic;

signalcondition_met:

std_logic;

signalnormal_count:

std_logic;

signalcall_type:

std_logic;

signalpush_or_pop_type:

std_logic;

signalvalid_to_move:

std_logic;

--

--Flagsignals

--

signalflag_type:

std_logic;

signalflag_write:

std_logic;

signalflag_enable:

std_logic;

signalzero_flag:

std_logic;

signalsel_shadow_zero:

std_logic;

signallow_zero:

std_logic;

signalhigh_zero:

std_logic;

signallow_zero_carry:

std_logic;

signalhigh_zero_carry:

std_logic;

signalzero_carry:

std_logic;

signalzero_fast_route:

std_logic;

signallow_parity:

std_logic;

signalhigh_parity:

std_logic;

signalparity_carry:

std_logic;

signalparity:

std_logic;

signalcarry_flag:

std_logic;

signalsel_parity:

std_logic;

signalsel_arith_carry:

std_logic;

signalsel_shift_carry:

std_logic;

signalsel_shadow_carry:

std_logic;

signalsel_carry:

std_logic_vector（3downto0）;

signalcarry_fast_route:

std_logic;

--

--Interruptsignals

--

signalactive_interrupt:

std_logic;

signalint_pulse:

std_logic;

signalclean_int:

std_logic;

signalshadow_carry:

std_logic;

signalshadow_zero:

std_logic;

signalint_enable:

std_logic;

signalint_update_enable:

std_logic;

signalint_enable_value:

std_logic;

signalinterrupt_ack_internal:

std_logic;

--

--ProgramCountersignals

--

signalpc:

std_logic_vector（9downto0）;

signalpc_vector:

std_logic_vector（9downto0）;

signalpc_vector_carry:

std_logic_vector（8downto0）;

signalinc_pc_vector:

std_logic_vector（9downto0）;

signalpc_value:

std_logic_vector（9downto0）;

signalpc_value_carry:

std_logic_vector（8downto0）;

signalinc_pc_value:

std_logic_vector（9downto0）;

signalpc_enable:

std_logic;

--

--DataRegistersignals

--

signalsx:

std_logic_vector（7downto0）;

signalsy:

std_logic_vector（7downto0）;

signalregister_type:

std_logic;

signalregister_write:

std_logic;

signalregister_enable:

std_logic;

signalsecond_operand:

std_logic_vector（7downto0）;

--

--ScratchPadMemorysignals

--

signalmemory_data:

std_logic_vector（7downto0）;

signalstore_data:

std_logic_vector（7downto0）;

signalmemory_type:

std_logic;

signalmemory_write:

std_logic;

signalmemory_enable:

std_logic;

--

--Stacksignals

--

signalstack_pop_data:

std_logic_vector（9downto0）;

signalstack_ram_data:

std_logic_vector（9downto0）;

signalstack_address:

std_logic_vector（4downto0）;

signalhalf_stack_address:

std_logic_vector（4downto0）;

signalstack_address_carry:

std_logic_vector（3downto0）;

signalnext_stack_address:

std_logic_vector（4downto0）;

signalstack_write_enable:

std_logic;

signalnot_active_interrupt:

std_logic;

--

--ALUsignals

--

signallogical_result:

std_logic_vector（7downto0）;

signallogical_value:

std_logic_vector（7downto0）;

signalsel_logical:

std_logic;

signalshift_result:

std_logic_vector（7downto0）;

signalshift_value:

std_logic_vector（7downto0）;

signalsel_shift:

std_logic;

signalhigh_shift_in:

std_logic;

signallow_shift_in:

std_logic;

signalshift_in:

std_logic;

signalshift_carry:

std_logic;

signalshift_carry_value:

std_logic;

signalarith_result:

std_logic_vector（7downto0）;

signalarith_value:

std_logic_vector（7downto0）;

signalhalf_arith:

std_logic_vector（7downto0）;

signalarith_internal_carry:

std_logic_vector（7downto0）;

signalsel_arith_carry_in:

std_logic;

signalarith_carry_in:

std_logic;

signalinvert_arith_carry:

std_logic;

signalarith_carry_out:

std_logic;

signalsel_arith:

std_logic;

signalarith_carry:

std_logic;

--

--ALUmultiplexersignals

--

signalinput_fetch_type:

std_logic;

signalsel_group:

std_logic;

signalalu_group:

std_logic_vector（7downto0）;

signalinput_group:

std_logic_vector（7downto0）;

signalalu_result:

std_logic_vector（7downto0）;

--

--readandwritestrobes

--

signalio_initial_decode:

std_logic;

signalwrite_active:

std_logic;

signalread_active:

std_logic;

--

--

------------------------------------------------------------------------------------

--

--AttributestodefineLUTcontentsduringimplementationforprimitivesnot

--containedwithingenerateloops.Ineachcasetheinformationisrepeated

--inthegenericmapforfunctionalsimulation

--

attributeINIT:

string;

attributeINIToft_state_lut:

labelis"1";

attributeINITofint_pulse_lut:

labelis"0080";

attributeINITofint_update_lut:

labelis"EAAA";

attributeINITofint_value_lut:

labelis"04";

attributeINITofmove_group_lut:

labelis"7400";

attributeINITofcondition_met_lut:

labelis"5A3C";

attributeINITofnormal_count_lut:

labelis"2F";

attributeINITofcall_type_lut:

labelis"1000";

attributeINITofpush_pop_lut:

labelis"5400";

attributeINITofvalid_move_lut:

labelis"D";

attributeINITofflag_type_lut:

labelis"41FC";

attributeINITofflag_enable_lut:

labelis"8";

attributeINIToflow_zero_lut:

labelis"0001";

attributeINITofhigh_zero_lut:

labelis"0001";

attributeINITofsel_shadow_zero_lut:

labelis"3F";

attributeINIToflow_parity_lut:

labelis"6996";

attributeINITofhigh_parity_lut:

labelis"6996";

attributeINITofsel_parity_lut:

labelis"F3FF";

attributeINITofsel_arith_carry_lut:

labelis"F3";

attributeINITofsel_shift_carry_lut:

labelis"C";

attributeINITofsel_shadow_carry_lut:

labelis"3";

attributeINITofregister_type_lut:

labelis"0145";

attributeINITofregister_enable_lut:

labelis"8";

attributeINITofmemory_type_lut:

labelis"0400";

attributeINITofmemory_enable_lut:

labelis"8000";

attributeINITofsel_logical_lut:

labelis"FFE2";

attributeINIToflow_shift_in_lut:

labelis"E4";

attributeINITofhigh_shift_in_lut:

labelis"E4";

attributeINITofshift_carry_lut:

labelis"E4";

attributeINITofsel_arith_lut:

labelis"1F";

attributeINITofinput_fetch_type_lut:

labelis"0002";

att

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