电气电子专业毕业设计外文翻译用SPMC75的PDC定时器做BLDC电机的速度检测.docx

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电气电子专业毕业设计外文翻译用SPMC75的PDC定时器做BLDC电机的速度检测.docx

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电气电子专业毕业设计外文翻译用SPMC75的PDC定时器做BLDC电机的速度检测.docx

电气电子专业毕业设计外文翻译用SPMC75的PDC定时器做BLDC电机的速度检测

XXXX大学

（外文翻译材料）

学院：

专业：

学生姓名：

指导教师：

BLDCMotorSpeedEstimationUsingPDCTimerModule

1SpeedCalculationofBLDC

1.1SummaryofBLDC

SincecurrentBLDChassubstitutedtheelectricalcommutatorforthemechanicalone,iteliminatesthedisadvantagesofnoise,spark,electromagneticdisturbance,shortlifetime,etc.NowBLDCisprovidedwithadvantagesofsimplestructure,dependableoperationandeasymaintenanceasACmotordoes,aswellasadvantagesofhighefficient,noexcitationcostandfunctionalspeedregulationastraditionalDCmotordoes.Soitiswidelyusedinvariousfieldsofindustrialcontrolnow.

1.2PDCModuleIntroduction

SPMC75F2413Aprovidestwochannelsof16bitPDC（PhaseDetectionControl,PDC）timersusedforcapturefunctionandPWMoperation.ItalsosupportspositiondetectionfeaturesforBrushless-DCmotorapplication.ThePDCtimersareverysuitableforbothmechanicalspeedcalculation,withACIandBLDCmotorincluded,andphasecommutationforchangingcurrentconductionaccordingtopositioninformation.Figure1-1showstheblockdiagramofentirePDCtimers,channel0andchannel1.FordetailsofPDCtimer’sspecification,pleaserefertoTable1-1.

Table1-1PDCTimer

Function

PDCTimer0

PDCTimer1

Clocksources

Internalclock:

FCK/1,FCK/4,FCK/16,FCK/64,FCK/256,FCK/1024

Externalclock:

TCLKA,TCLKB

Internalclock:

FCK/1,FCK/4,FCK/16,FCK/64,FCK/256,FCK/1024

Externalclock:

TCLKA,TCLKB

IOpins

TIO0A,TIO0B,TIO0C

TIO1A,TIO1B,TIO1C

Timergeneralregister

P_TMR0_TGRA,P_TMR0_TGRB,P_TMR0_TGRC

P_TMR1_TGRA,P_TMR1_TGRB,P_TMR1_TGRC

Timerbufferregister

P_TMR0_TBRA,P_TMR0_TBRB,P_TMR0_TBRC

P_TMR1_TBRA,P_TMR1_TBRB,P_TMR1_TBRC

Timerperiodandcounterregister

P_TMR0_TPR,P_TMR0_TCNT

P_TMR1_TPR,P_TMR1_TCNT

Capturesample

clock

Internalclock:

FCK/1,FCK/2,FCK/4,FCK/8

Internalclock:

FCK/1,FCK/2,FCK/4,FCK/8

Countingedge

Countonrising,falling,bothedge

Counterclearsource

ClearedonP_TMR0_TGRA,P_TMR0_TGRB,P_TMR0_TGRCcaptureinput.

ClearedonP_POS0_DectDatapositiondetectiondatachanges.

ClearedonP_TMR0_TPRcomparematches.

ClearedonP_TMR1_TGRA,P_TMR1_TGRB,P_TMR1_TGRCcaptureinput.

ClearedonP_POS1_DectDatapositiondetectiondatachanges.

ClearedonP_TMR1_TPRcomparematches.

Inputcapturefunction

Yes

PWM

compare

match

output

function

1output

Yes

0output

Yes

Output

Hold

Yes

Edge-alignedPWM

Yes

Center-alignedPWM

Yes

Phasecountingmode

Yes,phaseinputsareTCLKA/TCLKB

Yes,phaseinputsareTCLKC/TCLKD

Timerbufferoperation

Yes

ADconvertstarttrigger

P_TMR0_TGRAcomparematch

P_TMR1_TGRAcomparematch

Interruptsources

Timer0TPRinterrupt

Timer0TGRAinterrupt

Timer0TGRBinterrupt

Timer0TGRCinterrupt

Timer0PDCinterrupt

Timer0overflowinterrupt

Timer0underflowinterrupt

Timer1TPRinterrupt

Timer1TGRAinterrupt

Timer1TGRBinterrupt

Timer1TGRCinterrupt

Timer1PDCinterrupt

Timer1overflowinterrupt

Timer1underflowinterrupt

Figure1-1PDCTimersBlockDiagram

1.3PDCOperation

ThisnotemainlydepictsPDCapplicationinmotorspeedmeasurement.FordetailedPDCintroduction,pleasereferto“SPMC75F2413AProgrammingGuide”authoredbySunplus.

PDCmodulehasfourtypesofregisterstoperformspeedmeasurement:

TimercontrolregisterP_TMRx_Ctrl（x=0,1）,positiondetectioncontrolregisterP_POSx_DectCtrl（x=0,1）,inputoutputcontrolregisterP_TMRx_IOCtrl（x=0,1）,andtimerinterruptenableregisterP_TMRx_INT（x=0,1）.Where,P_TMRx_CtrlandP_POSx_DectCtrlareintroducedindetail.

1.31InputOutputControlRegister

P_TMRx_Ctrl（x=0,1）

B15

B14

B13

B12

B11

B10

R/W

SPCK

MODE

CLEGS

R/W

SPCK

MODE

CLEGS

Bit15:

SPCK:

Captureinputsampleclockselect.Thesebitsselectthecaptureinputsampleclock.Captureinputwillbesampledwithsampleclock.Pulsesshorterthanfoursampleclockswillbeconsideredinvalid,andwillbeignored.

00=FCK/1

01=FCK/2

10=FCK/4

11=FCK/8

Bit13:

MODE:

Modesselect.Thesebitsareusedtoselectthetimeroperationmodes.

0000=Normaloperation（continuouscounterupcounting）

0100=Phasecountingmode1

0101=Phasecountingmode2

0110=Phasecountingmode3

0111=Phasecountingmode4

1x0x=Edge-alignedPWMmode（continuouscounterupcounting,PWMoutput）

1x1x=Center-alignedPWMmode（continuouscounterup/downcounting,PWMoutput）

Bit9:

CLEGS:

Counterclearedgeselect.Thesebitsselectthecounterclearingedgewhentheclearingsourceisininputcapturemode.

00=donotclear

01=risingedge

10=fallingedge

11=bothedge

Bit7:

CCLS:

Counterclearsourceselect.ThesebitsselecttheTCNTcounterclearingsource.

000=TCNTclearingdisabled

001=TCNTclearedbyP_TMRx_TGRA（x=0,1）captureinput

010=TCNTclearedbyP_TMRx_TGRB（x=0,1）captureinput

011=TCNTclearedbyP_TMRx_TGRC（x=0,1）captureinput

100=TCNTclearedbyeveryP_POSx_DectData（x=0,1）change6times

101=TCNTclearedbyeveryP_POSx_DectData（x=0,1）change3times

110=TCNTclearedbyP_POSx_DectData（x=0,1）positiondetectiondatachange

111=TCNTclearedbyP_TMRx_TPR（x=0,1）comparematch

Bit4:

CKEGS:

Clockedgeselect,Thesebitsselecttheinputclockedge.Whentheinputclockiscountedusingbothedges,theinputclockperiodishalved.WhenFCK/1isselectedascounterclock,counterwillcountatrisingedgeifcountatbothedgesisselected.

00=Countatrisingedge

01=Countatfallingedge

1X=Countatbothedges

Bit2:

TMRPS:

Timerpre-scalarselect.ThesebitsselecttheTCNTcounterclocksource.Itcanbeselectedindependentlyforeachchannel.

000=CountsonFCK/1

001=CountsonFCK/4

010=CountsonFCK/16

011=CountsonFCK/64

100=CountsonFCK/256

101=CountsonFCK/1024

110=CountsonTCLKApininput

111=CountsonTCLKBpininput

Controlregisterconfiguration

P_TMRx_Ctrl（x=0,1）isusedfortheselectionofinputcaptureduringspeedmeasurement.Ratherthanbeingageneralinputsignal,theinputcaptureisaperiodbetweentwopositiondetectionchangestriggeredbyPDCinterrupt.Thisperiodmustbecountedwithacertainfrequencysupportedbyaclocksource.Thus,thecountersonthisfunctionmustbeconfigured.

MODE:

Selectatimeroperationmodeinsevenmodes.However,onlythenormaloperation（continuouscounterupcounting）modecanbeselectedinthisapplication,becausetheothersixmodesareallrelatedtophasecountingmodeorPWMmode.

CCLS:

SelectaTCNTcounterclearingsourcefromeightsettings.Inthisapplication,oneamongthethreecanbeset:

100,101or110,whichrespectivelyindicatesthatTCNTisclearedforonceevery6/3/1timesP_thePOSx_DectData（x=0,1）changes.Also,theycanbedescribedas:

TCNTisclearedforonceevery360/180/60electricaldegreerotationofBLDC.ThissettingiscriticalforconvertingelectricalrevolutiontomechanicalrevolutionandmeasuringtheBLDCspeed.

CKEGS:

Selecttheinputclockedge,whichcanberising,fallingorbothedges.Whentheinputclockiscountedusingbothedges,theinputclockperiodishalved.NotetocountthisfactoronduringtheBLDCspeedcalculation.

TMRPS:

SelecttheTCNTcounterclocksourcefromeightsettings.ThissettingdeterminestheprecisionandtherangeduringBLDCspeedmeasurement.Seetheexamplecodebelow:

P_TMR0_Ctrl,B.MODE=0;//NormalCountingmode

P_TMR0_Ctrl,B.CCLS=6;//TCNTclearedbyP_POSx_DectData（x=0,1）

//Eachtimepositiondetectiondatachange

P_TMR0_Ctrl,B.CKEGS=0;//Countingatrisingedge

P_TMR0_Ctrl,B.TMRPS=3;//SelectFCK/64clocksource

1.3.2PositionDetectionControlRegister

P_POSx_DectCtrl（x=0,1）

B15

B14

B13

B12

B11

B10

R/W

SPLCK

SPLMOD

SPLCNT

R/W

PDEN

SPDLY

Bit15:

SPLCK:

Samplingclockselect.SelectFCK/4,FCK/8,FCK/32,orFCK/128forpositionsamplingclock

00=FCK/4

01=FCK/8

10=FCK/32

11=FCK/128

Bit13:

SPLMOD:

Samplingmodeselect.Selectoneofthreemodes:

samplingwhenPWMsignalisactive（PWMison）,samplingregularly,orsamplingwhenlowerside（UN,VN,WN）phasesareconductingcurrent.

00=SamplewhenUPWM/VPWM/WPWMbitissetinP_TMRx_OutputCtrl（x=3,4）registerandgeneratethePWMwaveform

01=Sampleregularly

10=Samplewhenlowerphasesisinactivestateandconductingcurrent

11=Reserved

Bit11:

SPLCNT:

Samplingcountselect.Thesebitsselectthesamplingcountforthevalidexternalpositiondetectionsignals.Thepositionsignalsmustbesampledcontinuouslymatchasmanytimesasthesamplingcountset,forthepositionsignalstobeconsideredvalid.Thevalidsettingsarefrom1to15times.Notethatcount0and1areassumedtobeonetime.

Bit:

PDEN:

Positiondetectionenable.Thisbitenables/disablesthepositiondetectionfunctionforpositioninputpinsTIOA~C.Whenenabled,theinputsignalsofthesepinswillbesampledandtheresultswillbelatchedtoPDR[2:

0]bitsinPOS_DectDataregister.Whendisabled,PDR[2:

0]willremainitsstatus

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