EDA考试模块.docx
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EDA考试模块
EDA考试模块
useieee.std_logic_1164.all;
entityfull_adderis
port（Ai,Bi,Ci_1:
instd_logic;
Ci,Si:
outstd_logic）;
endfull_adder;
architecturefull_adder_archoffull_adderis
signalABC:
std_logic_vector（2downto0）;
signalY:
std_logic_vector（1downto0）;
begin
ABC<=Ai&Bi&Ci_1;
Y<="00"whenABC="000"else
"10"whenABC="001"else
"10"whenABC="010"else
"01"whenABC="011"else
"10"whenABC="100"else
"01"whenABC="101"else
"01"whenABC="110"else
"11";
Si<=Y
（1）;
Ci<=Y（0）;
endfull_adder_arch;
--full_adder4
libraryieee;
useieee.std_logic_1164.all;
entityfull_adderis
port（Ai,Bi,Ci_1:
instd_logic;
Ci,Si:
outstd_logic）;
endfull_adder;
architecturefull_adder_archoffull_adderis
signalABC:
std_logic_vector（2downto0）;
signalY:
std_logic_vector（1downto0）;
begin
ABC<=Ai&Bi&Ci_1;
process（ABC,Ai,Bi,Ci_1）
begin
IfABC="000"thenY<="00";
elsifABC="001"thenY<="10";
elsifABC="010"thenY<="10";
elsifABC="011"thenY<="01";
elsifABC="100"thenY<="10";
elsifABC="101"thenY<="01";
elsifABC="110"thenY<="01";
elseY<="11";
endif;
Si<=Y
（1）;
Ci<=Y（0）;
endprocess;
endfull_adder_arch;
--full_adder5
libraryieee;
useieee.std_logic_1164.all;
entityfull_adderis
port（Ai,Bi,Ci_1:
instd_logic;
Ci,Si:
outstd_logic）;
endfull_adder;
architecturefull_adder_archoffull_adderis
signalABC:
std_logic_vector（2downto0）;
signalY:
std_logic_vector（1downto0）;
begin
ABC<=Ai&Bi&Ci_1;
process（ABC,Ai,Bi,Ci_1）
begin
caseABCis
when"000"=>Y<="00";
when"001"=>Y<="10";
when"010"=>Y<="10";
when"011"=>Y<="01";
when"100"=>Y<="10";
when"101"=>Y<="01";
when"110"=>Y<="01";
when"111"=>Y<="11";
endcase;
Si<=Y
（1）;
Ci<=Y（0）;
endprocess;
endfull_adder_arch;
D锁存器
libraryieee;
useieee.std_logic_1164.all;
entitydff1is
port（D,clk:
instd_logic;
Q:
bufferstd_logic）;
enddff1;
architecturebehaveofdff1is
begin
process（clk,Q）
begin
ifclk'eventandclk='1'thenQ<=D;
endif;
endprocess;
endbehave;
JK触发器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityJK_chufais
Port（sd,rd,j,k,clk:
instd_logic;
q,qb:
outstd_logic
）;
endJK_chufa;
architecturebehaveofJK_chufais
signalqn:
std_logic;
begin
process（clk）
begin
ifsd='0'andrd='1'thenqn<='1';
elsifsd='1'andrd='0'thenqn<='0';
elsifsd='1'andrd='1'then
ifrising_edge（clk）then
qn<=（jandnotqn）or（notkandqn）;
endif;
endif;
endprocess;
q<=qn;
qb<=notqn;
endbehave;
10进制计数器
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_unsigned.all;
entitymodule_10is
port（ep,et,clr,load,clk:
instd_logic;
d:
instd_logic_vector（3downto0）;
co:
outstd_logic;
q:
bufferstd_logic_vector（3downto0）
）;
endmodule_10;
architecturebehaveofmodule_10is
begin
co<='1'when（q="1001"andep='1'andet='1'）else
'0';
process（clk,clr）
begin
if（clr='0'）thenq<="0000";
elsifrising_edge（clk）then
ifload='0'thenq<=d;
elsif（ep='1'andet='1'）then
if（q=9）thenq<="0000";
elseq<=q+1;
endif;
endif;
endif;
endprocess;
endbehave;
扫描显示
LIBRARYIEEE;
USEIEEE.STD_LOGIC_1164.ALL;
USEIEEE.STD_LOGIC_UNSIGNED.ALL;
USEIEEE.STD_LOGIC_ARITH.ALL;
ENTITYCNT8IS
PORT（CLK:
INSTD_LOGIC;
Q:
BUFFERSTD_LOGIC_VECTOR（2DOWNTO0））;
END;
ARCHITECTUREBEHOFCNT8IS
BEGIN
PROCESS（CLK）
BEGIN
IFRISING_EDGE（CLK）THEN
IFQ=7THENQ<="000";
ELSEQ<=Q+1;ENDIF;
ENDIF;
ENDPROCESS;
END;
libraryieee;
useieee.std_logic_1164.all;
entitydec7sis
port（a:
instd_logic_vector（2downto0）;
led7s:
outstd_logic_vector（6downto0））;
enddec7s;
architecturebehaveofdec7sis
begin
process（a）
begin
caseais
when"000"=>led7s<="1111111";
when"001"=>led7s<="1110000";
when"010"=>led7s<="1011111";--abcdefg
when"011"=>led7s<="1011011";
when"100"=>led7s<="0110011";
when"101"=>led7s<="1111001";
when"110"=>led7s<="1101101";
when"111"=>led7s<="0110000";
whenothers=>null;
endcase;
endprocess;
endbehave;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitydivxsis
port（clk20m:
instd_logic;
clk1:
outstd_logic）;
enddivxs;
architecturebhvofdivxsis
signalcount:
std_logic_vector（24downto0）;
begin
process（clk20m）
begin
ifrising_edge（clk20m）then
ifcount=1000then
count<=（others=>'0'）;
elsecount<=count+1;
endif;
ifcount<500then
clk1<='0';
elseclk1<='1';
endif;
endif;
endprocess;
endbhv;
交通灯
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitydiv_wxis
port（clk20m:
instd_logic;
clk1:
outstd_logic）;
enddiv_wx;
architecturebhvofdiv_wxis
signalcount:
std_logic_vector（24downto0）;
begin
process（clk20m）
begin
ifrising_edge（clk20m）then
ifcount=5000then
count<=（others=>'0'）;
elsecount<=count+1;
endif;
ifcount<2500then
clk1<='0';
elseclk1<='1';
endif;
endif;
endprocess;
endbhv;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entityseg7decis
port（din:
instd_logic_vector（3downto0）;
segout:
outstd_logic_vector（6downto0））;
endseg7dec;
architecturebehaveofseg7decis
begin
process（din）
begin
casedinis
when"0000"=>segout<="0111111";
when"0001"=>segout<="0000110";
when"0010"=>segout<="1011011";
when"0011"=>segout<="1001111";
when"0100"=>segout<="1100110";
when"0101"=>segout<="1101101";
when"0110"=>segout<="1111101";
when"0111"=>segout<="0000111";
when"1000"=>segout<="1111111";
when"1001"=>segout<="1101111";
whenothers=>null;
endcase;
endprocess;
endbehave;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitydivis
port（clk20m:
instd_logic;
clk1:
outstd_logic）;
enddiv;
architecturebhvofdivis
signalcount:
std_logic_vector（24downto0）;
begin
process（clk20m）
begin
ifrising_edge（clk20m）then
ifcount=10000000then
count<=（others=>'0'）;
elsecount<=count+1;
endif;
ifcount<5000000then
clk1<='0';
elseclk1<='1';
endif;
endif;
endprocess;
endbhv;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitytraffic_controlis
port（clk1hz,rst,clk_20mhz:
instd_logic;
--col:
outstd_logic;
--coh:
outstd_logic;
co:
outstd_logic_vector（1downto0）;
counter:
outstd_logic_vector（3downto0）;
q:
outstd_logic_vector（11downto0））;
endtraffic_control;
architecturebhvoftraffic_controlis
typestate_valueis（s1,s2,s3,s4）;
signalstate:
state_value;
signalcounterh:
std_logic_vector（3downto0）;
signalcounterl:
std_logic_vector（3downto0）;
begin
p1:
process（rst,clk1hz,clk_20mhz）
begin
ifrst='1'then
state<=s1;
counterh<="0010";
counterl<="0000";
q<="100001100001";
elsifrising_edge（clk1hz）then
casestateis
whens1=>ifcounterh="0000"andcounterl="0000"then
state<=s2;
q<="010001010001";
counterh<="0000";
counterl<="0011";
elsestate<=s1;
ifcounterl="0000"thencounterh<=counterh-1;counterl<="1001";
elsecounterl<=counterl-1;
endif;
endif;
whens2=>ifcounterh="0000"andcounterl="0000"then
state<=s3;
q<="001100001100";
counterh<="0001";
counterl<="0101";
elsestate<=s2;
ifcounterl="0000"thencounterh<=counterh-1;counterl<="1001";
elsecounterl<=counterl-1;
endif;
endif;
whens3=>ifcounterh="0000"andcounterl="0000"then
state<=s4;
q<="010100010100";
counterh<="0000";
counterl<="0011";
elsestate<=s3;
ifcounterl="0000"thencounterh<=counterh-1;counterl<="1001";
elsecounterl<=counterl-1;
endif;
endif;
whens4=>ifcounterh="0000"andcounterl="0000"then
state<=s1;
q<="100001100001";
counterh<="0010";
counterl<="0000";
elsestate<=s4;
ifcounterl="0000"thencounterh<=counterh-1;counterl<="1001";
elsecounterl<=counterl-1;
endif;
endif;
whenothers=>NULL;
endcase;
endif;
ifclk_20mhz='1'thencounter<=counterh;co<="10";
elsecounter<=counterl;co<="01";
endif;
endprocessp1;
endbhv;
数字钟
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitycounter_60is
port（en,rest,clk_1hz:
instd_logic;
--d:
instd_logic_vector（7downto0）;
qh:
bufferstd_logic_vector（3downto0）;
ql:
bufferstd_logic_vector（3downto0）;
co:
bufferstd_logic）;
endcounter_60;
architecturebhvofcounter_60is
begin
--co<='1'whenqh="0101"andql="1001"anden='1'else'0';
process（clk_1hz,rest,en）
begin
ifrest='0'thenqh<=（others=>'0'）;ql<=（others=>'0'）;
elsifrising_edge（clk_1hz）then
--ifset='1'then
--qh<=d（7downto4）;
--ql<=d（3downto0）;
ifen='1'then
ifql="1001"thenql<="0000";
ifqh="0101"then
qh<="0000";
co<='1';
elseqh<=qh+1;co<='0';
endif;
elseql<=ql+1;co<='0';
endif;
endif;
endif;
endprocess;
endbhv;
libraryieee;
useieee.std_logic_1164.all;
useieee.std_logic_arith.all;
useieee.std_logic_unsigned.all;
entitycounter_24is
port（en,rest,clk_1hz:
instd_logic;
--d:
instd_logic_vector（7downto0）;
qh:
bufferstd_logic_vector（3downto0）;
ql:
bufferstd_logic_vector（3downto0）;
co:
outstd_logic）;
endcounter_24;
architecturebhvofcounter_24is
begin
--co<='1'whenqh="0010"andql="0011"anden='1'else'0';
process（clk_1hz,rest,en）
begin
ifrest='0'thenqh<=（others=>'0'）;ql<=（others=>'0'）;
elsifrising_edge（clk_1hz）then
--ifset='1'then
--qh<=d（
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