单片机设计外文翻译.docx
《单片机设计外文翻译.docx》由会员分享,可在线阅读,更多相关《单片机设计外文翻译.docx(27页珍藏版)》请在冰豆网上搜索。
单片机设计外文翻译
附录A英文原文
1TheSerialPortInterfaceoftheLCDDriverIC
ThissectionwilldescribehowtocontroltheregistervalueoftheLCDdriverIContheLTM.
TheLCDandtouchpanelmoduleontheLTMisequippedwithaLCDdriverICtosupportthreedisplayresolutionandwithfunctionsofsourcedriver,serialportinterface,timingcontroller,andpowersupplycircuits.Tocontrolthesefunctions,userscanuseFPGAtoconfiguretheregistersintheLCDdriverICviaserialportinterface.
Also,thereisananalogtodigitalconverter(ADC)ontheLTMtoconverttheanalogX/YcoordinatesofthetouchpointtodigitaldataandoutputtoFPGAthroughtheserialportinterfaceoftheADC.BothLCDdriverICandADCserialportinterfacesareconnectedtotheFPGAviathe40-pinexpansionheaderandIDEcable.
BecauseofthelimitednumberofI/Oontheexpansionheader,theserialinterfacesoftheLCDdriverICandADCneedtosharethesameclock(ADC_DCLK)andchipenable(SCEN)signalI/Oontheexpansionheader.Toavoidboththeserialportinterfacesmayinterferewitheachotherwhensharingthesameclockandchipenablesignals,thechipenablesignal(CS),whichisinputtedintotheADCwillcomeupwithalogicinverterasshowninFigure1.1.
Figure1.1TheserialinterfaceoftheLCDtouchpanelmoduleandAD7843
Usersneedtopayattentioncontrollingthesharedsignalswhendesigningtheserialportinterfacecontroller.ThedetailedregistermapsoftheLCDdriverICarelistedinappendixchapter.ThespecificationsoftheserialportinterfaceoftheLCDdriverICaredescribedbelow.
TheLCDdriverICsupportsaclocksynchronousserialinterfaceastheinterfacetoaFPGAtoenableinstructionsetting.Pleasenoticethatinadditiontotheserialportinterfacesignals,NCLKinputshouldalsobeprovidedwhilesettingtheregisters.Figure1.2andTable1.1showtheframeformatandtimingdiagramoftheserialportinterface.TheLCDdriverICrecognizesthestartofdatatransferonthefallingedgeofSCENinputandstartsdatatransfer.Whensettinginstruction,theTPG110inputsthesettingvaluesviaSDAontherisingedgeofinputSCL.
Table1.1Thetimingparametersoftheserialportinterface
Item
Symbol
Condition
Min
Max
Unit
SDASetupTime
ts0
SCENtoSCL
150
ns
ts1
SDAtoSCL
150
ns
SDAHoldTime
th0
SCENtoSCL
150
ns
th1
SDAtoSCL
150
ns
PulseWidth
tw1l
SCLpulsewidth
160
ns
tw1h
SCLpulsewidth
160
ns
tw2
SCENpulseidth
1.0
ns
Clockduty
40
60
%
Thefirst6bits(A5~A0)specifytheaddressoftheregister.ThenextbitmeansRead/Writecommand.“0”iswritecommand.“1”isreadcommand.Then,thenextcycleisturn-roundcycle.Finally,thelast8bitsareforDatasetting(D7~D0).TheaddressanddataaretransferredfromtheMSBtoLSBsequentially.Thedataiswrittentotheregisterofassignedaddresswhen“Endoftransfer”isdetectedafterthe16thSCLrisingcycles.Dataisnotacceptediftherearelessormorethan16cyclesforonetransaction.
Figure1.2Theframeformatandtimingdiagramoftheserialportinterface
2InputtimingoftheLCDpaneldisplayfunction
ThissectionwilldescribethetimingspecificationoftheLCDsynchronoussignalsandRGBdata.
TodeterminethesequencingandthetimingoftheimagesignalsdisplayedontheLCDpanel,thecorrespondingsynchronoussignalsfromFPGAtotheLCDpanelshouldfollowthetimingspecification.
Figure2.1LCDhorizontaltimingspecification
Figure2.1illustratesthebasictimingrequirementsforeachrow(horizontal)thatisdisplayedontheLCDpanel.Anactive-lowpulseofspecificduration(timethpwinthefigure)isappliedtothehorizontalsynchronization(HD)inputoftheLCDpanel,whichsignifiestheendofonerowofdataandthestartofthenext.Thedata(RGB)inputsontheLCDpanelarenotvalidforatimeperiodcalledthehsyncbackporch(thbp)afterthehsyncpulseoccurs,whichisfollowedbythedisplayarea(thd).DuringthedatadisplayareatheRGBdatadriveseachpixelinturnacrosstherowbeingdisplayed.Also,duringtheperiodofthedatadisplayarea,thedataenablesignal(DEN)mustbedriventologichigh.Finally,thereisatimeperiodcalledthehsyncfrontporch(thfp)wheretheRGBsignalsarenotvalidagainbeforethenexthsyncpulsecanoccur.
Thetimingoftheverticalsynchronization(VD)isthesameasshowninFigure2.2,exceptthatavsyncpulsesignifiestheendofoneframeandthestartofthenext,andthedatareferstothesetofrowsintheframe(horizontaltiming).Table2.1and2.2showfordifferentresolutions,thedurationsoftimeperiodsthpw,thbp,thd,andthfpforbothhorizontalandverticaltiming.Finally,thetimingspecificationofthesynchronoussignalsisshownintheTable2.3.
Table2.1LCDhorizontaltimingparameters
Parameter
Symbol
PanelResolution
Unit
800xRGBx480
480xRGBx272
400xRGBx240
NCLK
NCLKFrequency
FNCLK
33.2
9
8.3
NCLK
Horizontalvaliddata
thd
800
480
400
NCLK
1HorizontalLine
th
1056
525
528
NCLK
HSYNCPulseWildth
Min
thbw
1
-
-
NCLK
Typ
Max
Hsyncbackporch
thbp
216
43
108
NCLK
Hsyncfrontporch
thfp
40
2
20
NCLK
DENEnableTime
tep
800
480
400
NCLK
Figure2.2LCDverticaltimingspecification
Table2.2LCDverticaltimingparameters
Parameter
Symbol
PanelResolution
Unit
800xRGBx480
480xRGBx272
400xRGBx240
H
Verticalvaliddata
tvd
480
272
240
H
Veritialperiod
tv
525
286
262
H
Veriticalblanking
tvbp
45
14
22
H
VSYNCPulseWildth
Min
tvpw
1
-
-
H
Typ
Max
Vsyncbackporch
tvbp
35
12
20
H
Vsyncfrontporch
tvfp
10
2
2
H
DENEnableTime
Tden
480
272
240
H
Table2.3ThetimingparametersoftheLCDsynchronoussignals
Parameter
Symbol
Min
Unit
NCLKperiod
PWclk
25
ns
NCLKpulsehighperiod
PWH
10
ns
NCLKpulselowperiod
PWL
10
ns
HD,VD,DEN,datasetuptime
tds
5
ns
HD,VD,DEN,dataholdtime
tdh
5
ns
3TheserialinterfaceoftheADconverter
ThissectionwilldescribehowtoobtaintheX/YcoordinatesofthetouchpointfromtheADconverter.
TheLTMalsoequippedwithanAnalogDevicesAD7843touchscreendigitizerchip.TheAD7843isa12-bitanalogtodigitalconverter(ADC)fordigitizingxandycoordinatesoftouchpointsappliedtothetouchscreen.ThecoordinatesofthetouchpointstoredintheAD7843canbeobtainedbytheserialportinterface.
ToobtainthecoordinatefromtheADC,thefirstthingusersneedtodoismonitortheinterruptsignalADC_PENIRQ_noutputtedfromtheADC.Byconnectingapullhighresistor,theADC_PENIRQ_noutputremainshighnormally.WhenthetouchscreenconnectedtotheADCistouchedviaapenorfinger,theADC_PENIRQ_noutputgoeslow,initiatinganinterrupttoaFPGAthatcantheninstructacontrolwordtobewrittentotheADCviatheserialportinterface.
ThecontrolwordprovidedtotheADCviatheDINpinisshowninFigure3.1.Thisprovidestheconversionstart,channeladdressing,ADCconversionresolution,configuration,andpower-downoftheADC.ThedetailedinformationontheorderanddescriptionofthesecontrolbitscanbefoundfromthedatasheetoftheADCintheDATASHEETfolderontheLTMSystemCD-ROM.
Figure3.1Controlregisterbitfunctiondescription
Figure3.2showsthetypicaloperationoftheserialinterfaceoftheADC.TheserialclockprovidestheconversionclockandalsocontrolsthetransferofinformationtoandfromtheADC.Onecompleteconversioncanbeachievedwith24ADC_DCLKcycles.ThedetailedbehavioroftheserialportinterfacecanbefoundinthedatasheetoftheADC.Notethattheclock(ADC_DCLK)andchipenablesignals(SCEN)oftheserialportinterfaceSHRAEthesamesignalI/OwithLCDdriverIC.UsersshouldavoidcontrollingtheLCDdriverICandADCatthesametimewhendesigningtheserialportinterfacecontroller.Also,becausethechipenablesignal(SCEN)inputtedtotheADCcomesupwithalogicinverter,thelogicleveloftheSCENshouldbeinversewhenitisusedtocontroltheADC.
Figure3.2Conversiontimingoftheserialportinterface
4BlockDiagramoftheEphotoDesign
ThissectionwilldescribetheblockdiagramoftheEphotodemonstrationtohelpusersinreadingthecodeprovided.
Figure4.1showstheblockdiagramoftheEPhotodemonstration.AssoonasthebitstreamisdownloadedintotheFPGA,theregistervaluesoftheLCDdriverICusingtocontroltheLCDdisplayfunctionwillbeconfiguredbytheLCD_SPI_Controllerblock,whichusestheserialportinterfacetocommunicatewiththeLCDdriverIC.Meanwhile,theFlash_to_SDRAM_ControllerblockwillreadtheRGBdataofonepicturestoredintheFlash,andthenwritethedataintoSDRAMbuffer.Accordingly,boththesynchronouscontrolsignalsandthepicturedatastoredintheSDRAMbufferwillbesenttotheLTMviatheLCD_Timing_Controllerblock.
WhenuserstouchLTMscreens,thexandycoordinatesofthetouchpointwillbeobtainedbytheADC_SPI_ControllerblockthroughtheADCserialportinterface.ThentheTouch_Point_Detectorblockwilldeterminewhetherthesecoordinatesareinaspecificrange.Ifthecoordinatesfittherange,theTouch_Point_DetectorblockwillcontroltheFlash_to_SDRAM_Controllerblocktoreadthenextorpreviouspicture'sdatafromtheFlashandrepeatthestepsasmentionedbeforetocommandtheLTMtodisplaythenextorpreviouspicture.
Figure4.1TheblockdiagramoftheEphotodemonstration
4SDRAMControllerSimulationModel
TheSDRAMcontrollerdesignfilesgeneratedbySOPCBuilderaresuitableforbothsynthesisandsimulation.Somesimulationfeaturesareimplementedinthe