TMS320x2833x Multichannel Buffered Serial Port McBSP Reference Guide第六章英文Word文档下载推荐.docx

TMS320x2833x Multichannel Buffered Serial Port McBSP Reference Guide第六章英文Word文档下载推荐.docx

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6.3BitsUsedtoEnableandConfiguretheClockStopMode...............60

6.4ClockStopModeTimingDiagrams.............................................61

6.5ProcedureforConfiguringaMcBSPforSPIOperation..................63

6.6McBSPastheSPIMaster...........................................................63

6.7McBSPasanSPISlave..............................................................65

6.1SPIProtocol

TheSPIprotocolisamaster-slaveconfigurationwithonemasterdeviceandoneormoreslavedevices.Theinterfaceconsistsofthefollowingfoursignals:

1、Serialdatainput（alsoreferredtoasmasterin/slaveout,orMISO）

2、Serialdataoutput（alsoreferredtoasmasterout/slavein,orMOSI）

3、Shift-clock（alsoreferredtoasSCK）

4、Slave-enablesignal（alsoreferredtoasSS）

AtypicalSPIinterfacewithasingleslavedeviceisshowninFigure6-1.

Figure6-1.TypicalSPIInterface

Themasterdevicecontrolstheflowofcommunicationbyprovidingshift-clockandslave-enablesignals.Theslave-enablesignalisanoptionalactive-lowsignalthatenablestheserialdatainputandoutputoftheslavedevice（devicenotsendingouttheclock）.

Intheabsenceofadedicatedslave-enablesignal,communicationbetweenthemasterandslaveisdeterminedbythepresenceorabsenceofanactiveshift-clock.WhentheMcBSPisoperatinginSPImastermodeandtheSSsignalisnotusedbytheslaveSPIport,theslavedevicemustremainenabledatalltimes,andmultipleslavescannotbeused.

6.2ClockStopMode

TheclockstopmodeoftheMcBSPprovidescompatibilitywiththeSPIprotocol.WhentheMcBSPisconfiguredinclockstopmode,thetransmitterandreceiverareinternallysynchronizedsothattheMcBSPfunctionsasanSPImasterorslavedevice.Thetransmitclocksignal（CLKX）correspondstotheserialclocksignal（SCK）oftheSPIprotocol,whilethetransmitframe-synchronizationsignal（FSX）isusedastheslave-enablesignal（SS）.

Thereceiveclocksignal（MCLKR）andreceiveframe-synchronizationsignal（FSR）arenotusedintheclockstopmodebecausethesesignalsareinternallyconnectedtotheirtransmitcounterparts,CLKXandFSX.

6.3BitsUsedtoEnableandConfiguretheClockStopMode

ThebitsrequiredtoconfiguretheMcBSPasanSPIdeviceareintroducedinTable6-1.Table6-2showshowthevariouscombinationsoftheCLKSTPbitandthepolaritybitsCLKXPandCLKRPcreatefourpossibleclockstopmodeconfigurations.ThetimingdiagramsinSection6.4showtheeffectsofCLKSTP,CLKXP,andCLKRP.

Table6-1.BitsUsedtoEnableandConfiguretheClockStopMode

Table6-2.EffectsofCLKSTP,CLKXP,andCLKRPontheClockScheme

6.4ClockStopModeTimingDiagrams

Thetimingdiagramsforthefourpossibleclockstopmodeconfigurationsareshownhere.Noticethattheframe-synchronizationsignalusedinclockstopmodeisactivethroughouttheentiretransmissionasaslave-enablesignal.Althoughthetimingdiagramsshow8-bittransfers,thepacketlengthcanbesetto8,12,16,20,24,or32bitsperpacket.ThereceivepacketlengthisselectedwiththeRWDLEN1bitsofRCR1,andthetransmitpacketlengthisselectedwiththeXWDLEN1bitsofXCR1.Forclockstopmode,thevaluesofRWDLEN1andXWDLEN1mustbethesamebecausetheMcBSPtransmitandreceivecircuitsaresynchronizedtoasingleclock.

Note:

Evenifmultiplewordsareconsecutivelytransferred,theCLKXsignalisalwaysstoppedandtheFSXsignalreturnstotheinactivestateafterapackettransfer.Whenconsecutivepackettransfersareperformed,thisleadstoaminimumidletimeoftwobit-periodsbetweeneachpackettransfer.

Figure6-2.SPITransferWithCLKSTP=10b（NoClockDelay）,CLKXP=0,andCLKRP=0

AIftheMcBSPistheSPImaster（CLKXM=1）,MOSI=DX.IftheMcBSPistheSPIslave（CLKXM=0）,MOSI=DR.

BIftheMcBSPistheSPImaster（CLKXM=1）,MISO=DR.IftheMcBSPistheSPIslave（CLKXM=0）,MISO=DX.

Figure6-3.SPITransferWithCLKSTP=11b（ClockDelay）,CLKXP=0,CLKRP=1

Figure6-4.SPITransferWithCLKSTP=10b（NoClockDelay）,CLKXP=1,andCLKRP=0

Figure6-5.SPITransferWithCLKSTP=11b（ClockDelay）,CLKXP=1,CLKRP=1

AIftheMcBSPistheSPImaster（CLKXM=1）,MOSI=DX.IftheMcBSPistheSPIslave（CLKXM=0）,MOSI=DR.

BIftheMcBSPistheSPImaster（CLKXM=1）,MISO=DR.IftheMcBSPistheSPIslave（CLKXM=0）,MISO=DX.

6.5ProcedureforConfiguringaMcBSPforSPIOperation

ToconfiguretheMcBSPforSPImasterorslaveoperation:

Step1.Placethetransmitterandreceiverinreset.

Clearthetransmitterresetbit（XRST=0）inSPCR2toresetthetransmitter.Clearthereceiverresetbit（RRST=0）inSPCR1toresetthereceiver.

Step2.Placethesamplerategeneratorinreset.

Clearthesamplerategeneratorresetbit（GRST=0）inSPCR2toresetthesamplerategenerator.

Step3.ProgramregistersthataffectSPIoperation.

ProgramtheappropriateMcBSPregisterstoconfiguretheMcBSPforproperoperationasanSPImasteroranSPIslave.Foralistofimportantbitssettings,seeoneofthefollowingtopics:

1、McBSPastheSPIMaster（Section6.6）

2、McBSPasanSPISlave（Section6.7）

Step4.Enablethesamplerategenerator.

Toreleasethesamplerategeneratorfromreset,setthesamplerategeneratorresetbit（GRST=1）inSPCR2.MakesurethatduringthewritetoSPCR2,youonlymodifyGRST.Otherwise,youmodifytheMcBSPconfigurationyouselectedinthepreviousstep.

Step5.Enablethetransmitterandreceiver.

Afterthesamplerategeneratorisreleasedfromreset,waittwosamplerategeneratorclockperiodsfortheMcBSPlogictostabilize.IftheCPUservicestheMcBSPtransmitandreceivebuffers,thenyoucanimmediatelyenablethetransmitter（XRST=1inSPCR2）andenablethereceiver（RRST=1inSPCR1）.IftheDMAcontrollerservicestheMcBSPtransmitandreceivebuffers,thenyoumustfirstconfiguretheDMAcontroller（thisincludesenablingthechannelsthatservicetheMcBSPbuffers）.WhentheDMAcontrollerisready,makeXRST=1andRRST=1.Ineithercase,makesureyouonlychangeXRSTandRRSTwhenyouwritetoSPCR2andSPCR1.Otherwise,youmodifythebitsettingsyouselectedearlierinthisprocedure.Afterthetransmitterandreceiverarereleasedfromreset,waittwosamplerategeneratorclockperiodsfortheMcBSPlogictostabilize.

Step6.Ifnecessary,enabletheframe-synchronizationlogicofthesamplerategenerator.

Aftertherequireddataacquisitionsetupisdone（DXR[1,2]isloadedwithdata）,setFRST=1ifaninternallygeneratedframe-synchronizationpulseisrequired（thatis,iftheMcBSPistheSPImaster）.

6.6McBSPastheSPIMaster

AnSPIinterfacewiththeMcBSPusedasthemasterisshowninFigure6-6.WhentheMcBSPisconfiguredasamaster,thetransmitoutputsignal（DX）isusedastheMOSIsignaloftheSPIprotocolandthereceiveinputsignal（DR）isusedastheMISOsignal.

TheregisterbitvaluesrequiredtoconfiguretheMcBSPasamasterarelistedinTable6-3.Afterthetablearemoredetailsabouttheconfigurationrequirements.

Figure6-6.SPIInterfacewithMcBSPUsedasMaster

Table6-3.BitValuesRequiredtoConfiguretheMcBSPasanSPIMaster

WhentheMcBSPfunctionsastheSPImaster,itcontrolsthetransmissionofdatabyproducingtheserialclocksignal.TheclocksignalontheMCLKXpinisenabledonlyduringpackettransfers.Whenpacketsarenotbeingtransferred,theMCLKXpinremainshighorlowdependingonthepolarityused.

ForSPImasteroperation,theMCLKXpinmustbeconfiguredasanoutput.ThesamplerategeneratoristhenusedtoderivetheCLKXsignalfromtheCPUclock.TheclockstopmodeinternallyconnectstheMCLKXpintotheMCLKRsignalsothatnoexternalsignalconnectionisrequiredontheMCLKRpinandboththetransmitandreceivecircuitsareclockedbythemasterclock（CLKX）.

ThedatadelayparametersoftheMcBSP（XDATDLYandRDATDLY）mustbesetto1forproperSPImasteroperation.Adatadelayvalueof0or2isundefinedintheclockstopmode.

TheMcBSPcanalsoprovideaslave-enablesignal（SS_）ontheFSXpin.Ifaslave-enablesignalisrequired,theFSXpinmustbeconfiguredasanoutputandthetransmittermustbeconfiguredsothataframe-synchronizationpulseisgeneratedautomaticallyeachtimeapacketistransmitted（FSGM=0）.ThepolarityoftheFSXpinisprogrammablehighorlow;

however,inmostcasesthepinmustbeconfiguredactivelow.

WhentheMcBSPisconfiguredasdescribedforSPI-masteroperation,thebitfieldsforframe-synchronizationpulsewidth（FWID）andframe-synchronizationperiod（FPER）areoverridden,andcustomframe-synchronizationwaveformsarenotallowed.ToseetheresultingwaveformproducedontheFSXpin,seethetimingdiagramsinSection6.4.Thesignalbecomesactivebeforethefirstbitofapackettrans